modelsim 6.2b 的初次使用

module count_tp;
reg clk,reset;
wire [3:0] out;

parameter DELY=100;
count4 mycount(out,reset,clk);
always #(DELY/2) clk=~clk;
initial begin
    clk=0;reset=0;
#DELY reset=1;
#DELY reset=0;
#(DELY*20) $finish;
end
initial $monitor($time,,,
"clk=%d reset=%d out=%d",clk,reset,out);
endmodule

module count4 (out,reset,clk);
output[3:0] out;
input reset,clk;
reg [3:0] out;
always @(posedge clk)
   begin
       if(reset) out=0;
       else   out=out+1;
   end
endmodule   


-- Loading package standard
** Error: D:/Modeltech_6.2b/examples/count_tp.v(1): near "module": expecting: ARCHITECTURE CONFIGURATION
ENTITY LIBRARY PACKAGE USE
** Error: D:/Modeltech_6.2b/examples/count_tp.v(3): near "3:0]": (vcom-113) Mantissa part of based integer
literal terminates with ']'; should be ':'.
** Error: D:/Modeltech_6.2b/examples/count_tp.v(18): near "3:0]": (vcom-113) Mantissa part of based integer
literal terminates with ']'; should be ':'.
** Error: D:/Modeltech_6.2b/examples/count_tp.v(20): near "3:0]": (vcom-113) Mantissa part of based integer
literal terminates with ']'; should be ':'.

网上搜索了半天不得法门，非常郁闷
今天无聊，就在那相相啊，瞎捣鼓，终于知道啥问题了
编译菜单出来后，发现有个项目，properties， 打开后，选择了，general，再选 verilog，并选OK
再 编译
哈哈，绿色的提示出来了，OL，顺利编译

仔细想了下，应该是这个么原因：
工程默认是用VHDL 的，所以在编译时，应该先择 verilog地