verilog behavioral modeling--branch statement

conditional statement

case statement

 

1. conditional statement

    if(expression)

        statement_or_null[else statement_or_null]

    | if_else_if_statement

 

If the expression evaluates to true(that is ,has a nonzero know value),the first statement shall be executed.

If it evaluates to flase(that is ,has a zero value or the value is x or z) , the first statement shall not execute.

If there is an else statement and expression is false , the else statement shall be executed.

 

  if-else-if construct(mutiway decision statement)

      The expression shall be evaluated in order.If any expression is true,the statement associated with it shall be executed,and this shall terminate the whole chain.

  Each statement is either a single statement or a block of statement.

 

2.case statement(multiway decision statement)

   The case expression given in parentheses shall be evaluated exactly once and before any of the case item expression.

   The case item expressions shall be evaluated and compared in the exactly order in which they are given.

   If there is a default case item, it is ignored during this linear search.

   During the linear search , if one of the case item shall be executed, and the linear search shall terminate.

   If all comparisions fail and the default item is given,then the default item statement shall be executed .

  If the default statement is not given and all of the comparision fail, then none of the case item statements shall be executed.

    linear search ??

 

  The case statement differs from the multiway if-else-if construct in two important ways:

   a) The condition expression in the if-else-if construct are more general than comparing one expression with several others,as in the case statement.

  b)  The case statement provides a definitive result when there are x and z values in an expression.

         In a case expression comparison,the comparison only succeeds when each bit mathes exactly with respect to the valule 0 、 1、x and z.

         As a consequence, care is needed in  specifying the expression in the case statement.

         The bit length of all the expression shall be equal so that exact bitwise matching can be performed.

         The length of all the case item expressions as well as the case expression in the parentheses,shall be made equal to the length of the longest case expression and case item expression.

         If any of these expression is unsigned , then all of them shall be treated as unsigned.

         If all of these expressions are signed, then they shall be treated as signed.

 

3.casex / casez --dont care

   case x --- treats x /z as do-not-care condition

   case z ---treats z as do-not-care condition

 

   allows the use of mark(?) in place of z it these case statements(可以用来实现具有优先级的分支选择类似if-else-if)

   eg:

        reg [7:0] ir;

        casez(ir)

           8'b1???????:instruction(ir);

           8'b01??????:instruction(ir);

           8'b001?????:instruction(ir);

           8'b0001????:instruction(ir);

           8'b00001???:instruction(ir);

      endcase

      constant expression in case statement(也可以实现priority,觉得相比于 mark（？）实现priority，这个更好 )

       reg [2:0] encode;

       case(1)

          encode[2]: $display("Select line 2");

          encode[1]:$display("Select line 1");

          encode[0]:$display("Select line 0");

          default $display("Error:one of the bits expected ON");

         endcase

转载于:https://www.cnblogs.com/chip/p/4074522.html