RS232串口通信

特权实验视频代码

module my_uart_top(
    clk, rst_n,
    rs232_rx,rs232_tx
    );
input clk;
input rst_n;
input rs232_rx;
output rs232_tx;

wire bps_start1,bps_start2;
wire clk_bps1,clk_bps2;
wire [7:0] rx_data;
wire rx_int;

speed_select   speed_rx(
       .clk(clk),
       .rst_n(rst_n),
       .bps_start(bps_start1),
       .clk_bps(clk_bps1)
      );

my_uart_rx   my_uart_rx(
       .clk(clk),
       .rst_n(rst_n),
       .rs232_rx(rs232_rx),
       .rx_data(rx_data),
       .rx_int(rx_int),
       .clk_bps(clk_bps1),
       .bps_start(bps_start1)
      );
   
speed_select   speed_tx(
       .clk(clk),
       .rst_n(rst_n),
       .bps_start(bps_start2),
       .clk_bps(clk_bps2)
      );    
my_uart_tx   my_uart_tx(
       .clk(clk),
       .rst_n(rst_n),
       .rx_data(rx_data),
       .rx_int(rx_int),
       .bps_start(bps_start2),
       .clk_bps(clk_bps2),
       .rs232_tx(rs232_tx)
      );

endmodule
    
 module my_uart_rx(
    clk,rst_n,
    rs232_rx,rx_data,rx_int,
    clk_bps,bps_start
   );

input clk;
input rst_n;
input rs232_rx;
input clk_bps;
output bps_start;
output [7:0] rx_data;
output rx_int;

reg rs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3;
wire neg_rs232_rx;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   rs232_rx0 <= 1'b0;
   rs232_rx1 <= 1'b0;
   rs232_rx2 <= 1'b0;
   rs232_rx3 <= 1'b0;
  end
 else begin
   rs232_rx0 <= rs232_rx;
   rs232_rx1 <= rs232_rx0;
   rs232_rx2 <= rs232_rx1;
   rs232_rx3 <= rs232_rx2;
  end

assign neg_rs232_rx = rs232_rx3 & rs232_rx2 & ~rs232_rx1 & ~rs232_rx0;
//----------------------------------------------------------------------
reg bps_start_r;
reg [3:0] num;
reg rx_int;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   bps_start_r <= 1'bz;
   rx_int <= 1'b0;
  end
 else if(neg_rs232_rx) begin
   bps_start_r <= 1'b1;
   rx_int <= 1'b1;
  end
 else if(num == 4'd12) begin
   bps_start_r <= 1'b0;
   rx_int <= 1'b0;
  end

assign bps_start = bps_start_r;

reg [7:0] rx_data_r;
reg [7:0] rx_temp_data;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   rx_temp_data <= 8'd0;
   num <= 4'd0;
   rx_data_r <= 8'd0;
  end
 else if(rx_int) begin
  if(clk_bps) begin
     num <= num +1'b1;
     case (num)
       4'd1: rx_temp_data[0] <= rs232_rx;
       4'd2: rx_temp_data[1] <= rs232_rx;
       4'd3: rx_temp_data[2] <= rs232_rx;
       4'd4: rx_temp_data[3] <= rs232_rx;
       4'd5: rx_temp_data[4] <= rs232_rx;
       4'd6: rx_temp_data[5] <= rs232_rx;
       4'd7: rx_temp_data[6] <= rs232_rx;
       4'd8: rx_temp_data[7] <= rs232_rx;
       default: ;
       endcase
    end
   else if(num == 4'd12) begin
     num <= 4'd0;
     rx_data_r <= rx_temp_data;
    end
   end
assign rx_data = rx_data_r;
 
endmodule

module my_uart_tx(
    clk,rst_n,
    rx_data,rx_int,rs232_tx,
    clk_bps,bps_start
   );

input clk;
input rst_n;
input clk_bps;
input [7:0] rx_data;
input rx_int;
output rs232_tx;
output bps_start;

reg rx_int0,rx_int1,rx_int2;
wire neg_rx_int;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   rx_int0 <= 1'b0;
   rx_int1 <= 1'b0;
   rx_int2 <= 1'b0;
  end
 else begin
   rx_int0 <= rx_int;
   rx_int1 <= rx_int0;
   rx_int2 <= rx_int1;
  end

assign neg_rx_int = ~rx_int1 & rx_int2;

reg [7:0] tx_data;

reg bps_start_r;
reg tx_en;
reg [3:0] num;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   bps_start_r <= 1'bz;
   tx_en <= 1'b0;
   tx_data <= 8'd0;
  end
 else if (neg_rx_int) begin
   bps_start_r <= 1'b1;
   tx_data <= rx_data;
   tx_en <= 1'b1;
  end
 else if(num == 4'd11) begin
   bps_start_r <= 1'b0;
   tx_en <= 1'b0;
  end

assign bps_start = bps_start_r;

reg rs232_tx_r;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
   num <= 4'd0;
   rs232_tx_r <= 1'b1;
  end
 else if(tx_en) begin
   if(clk_bps) begin
     num <= num + 1'b1;
     case (num)
      4'd0: rs232_tx_r <= 1'b0;
      4'd1: rs232_tx_r <= tx_data[0];
      4'd2: rs232_tx_r <= tx_data[1];
      4'd3: rs232_tx_r <= tx_data[2];
      4'd4: rs232_tx_r <= tx_data[3];
      4'd5: rs232_tx_r <= tx_data[4];
      4'd6: rs232_tx_r <= tx_data[5];
      4'd7: rs232_tx_r <= tx_data[6];
      4'd8: rs232_tx_r <= tx_data[7];
      4'd9: rs232_tx_r <= 1'b1;
      default: rs232_tx_r <= 1'b1;
     endcase
   end
  else if(num == 4'd11) num <= 4'd0;
 end

assign rs232_tx = rs232_tx_r;

endmodule

module speed_select(
    clk,rst_n,
    bps_start,clk_bps
   );
input clk;
input rst_n;
input bps_start;
output clk_bps;

`define  BPS_PARA  5207
`define  BPS_PARA_2  2603

reg [12:0] cnt;
reg clk_bps_r;

reg [2:0] uart_ctrl;

always @ (posedge clk or negedge rst_n)
 if(!rst_n) cnt <= 13'd0;
 else if ((cnt == `BPS_PARA) || !bps_start) cnt <= 13'd0;
 else cnt <= cnt + 1'd1;

always @ (posedge clk or negedge rst_n) 
 if(!rst_n) clk_bps_r <= 1'b0;
 else if(cnt == `BPS_PARA_2) clk_bps_r <= 1'b1;
 else clk_bps_r <= 1'b0;

assign clk_bps = clk_bps_r;

endmodule  

转载于:https://www.cnblogs.com/hdu-Qmn/archive/2011/08/17/2143470.html