YCrCb444转换成YCrCb422随笔

　　在项目中，RGB先转换成YCrCb444，然后需要YCrCb444转换成YCrCb422，这此记录下来。以下就是对应源代码。

`timescale 1ns/1ps

module YUV444_422 (
 input clk,
 input rst_n,
 input iVsync,
 input iHsync,
 input iDVAL,
 
 input[23:0] YUV444_D,
 
 output reg oVsync,
 output reg oHsync,
 output reg oDVAL,
 output reg[15:0] YUV422_D
 );
 
reg[23:0] YUV444_Dbuf0,YUV444_Dbuf1,YUV444_Dbuf2,YUV444_Dbuf3,YUV444_Dbuf4,YUV444_Dbuf5,YUV444_Dbuf6;
reg iDVAL_reg0,iDVAL_reg1,iDVAL_reg2,iDVAL_reg3,iDVAL_reg4,iDVAL_reg5,iDVAL_reg6;
reg iVsync_reg0,iVsync_reg1,iVsync_reg2,iVsync_reg3,iVsync_reg4,iVsync_reg5,iVsync_reg6;
reg iHsync_reg0,iHsync_reg1,iHsync_reg2,iHsync_reg3,iHsync_reg4,iHsync_reg5,iHsync_reg6;

reg[9:0] YUV444_Cr_Sum0,YUV444_Cr_Sum1,YUV444_Cr_Sum2;
reg[9:0] YUV444_Cb_Sum0,YUV444_Cb_Sum1,YUV444_Cb_Sum2;

reg[7:0] Cr,Cb,Crbuf;

reg Sel;

always@(posedge clk)
begin
iDVAL_reg0 <= iDVAL;
iDVAL_reg1 <= iDVAL_reg0;
iDVAL_reg2 <= iDVAL_reg1;
iDVAL_reg3 <= iDVAL_reg2;
iDVAL_reg4 <= iDVAL_reg3;
iDVAL_reg5 <= iDVAL_reg4;
iDVAL_reg6 <= iDVAL_reg5;
oDVAL <= iDVAL_reg3;
end

always@(posedge clk )
begin
iVsync_reg0 <= iVsync;
iVsync_reg1 <= iVsync_reg0;
iVsync_reg2 <= iVsync_reg1;
iVsync_reg3 <= iVsync_reg2;
iVsync_reg4 <= iVsync_reg3;
iVsync_reg5 <= iVsync_reg4;
iVsync_reg6 <= iVsync_reg5;
oVsync <= iVsync_reg3;
end

always@(posedge clk)
begin
iHsync_reg0 <= iHsync;
iHsync_reg1 <= iHsync_reg0;
iHsync_reg2 <= iHsync_reg1;
iHsync_reg3 <= iHsync_reg2;
iHsync_reg4 <= iHsync_reg3;
iHsync_reg5 <= iHsync_reg4;
iHsync_reg6 <= iHsync_reg5;
oHsync <= iHsync_reg3;
end

always@(posedge clk )
begin
YUV444_Dbuf0 <= YUV444_D;
YUV444_Dbuf1 <= YUV444_Dbuf0;
YUV444_Dbuf2 <= YUV444_Dbuf1;
YUV444_Dbuf3 <= YUV444_Dbuf2;
YUV444_Dbuf4 <= YUV444_Dbuf3;
YUV444_Dbuf5 <= YUV444_Dbuf4;
YUV444_Dbuf6 <= YUV444_Dbuf5;
end

always@(posedge clk )
begin
YUV444_Cr_Sum0 <= YUV444_Dbuf0[7:0] + YUV444_Dbuf1[7:0] ;
end

always@(posedge clk )
begin
YUV444_Cb_Sum0 <= YUV444_Dbuf0[15:8] + YUV444_Dbuf1[15:8];
end

always@(posedge clk)
Cr <= YUV444_Cr_Sum0[8:1];

always@(posedge clk)
Cb <= YUV444_Cb_Sum0[8:1];

always@(posedge clk or  negedge rst_n)
begin
if(~rst_n)
 Sel <= 1'b0;
else if(iDVAL_reg3)
 Sel <= ~Sel;
else
 Sel <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
 YUV422_D <= 16'd0;
else if(iDVAL_reg3)
 begin
 YUV422_D[15:8] <= YUV444_Dbuf3[23:16];
 if(!Sel)
  begin
  YUV422_D[7:0] <= Cb;
  Crbuf <= Cr;
  end
 else
  YUV422_D[7:0] <= Crbuf;
 end
end

endmodule

转载于:https://www.cnblogs.com/wuqingjianke/p/3441864.html