Intel RDT

首先 spec， 从671页看起

https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf

 

1. CAT 

https://software.intel.com/en-us/articles/introduction-to-cache-allocation-technology

Here is the link to recorded presentation from Tony:

https://soco.intel.com/docs/DOC-2307814

2. CDP

https://software.intel.com/en-us/articles/introduction-to-code-and-data-prioritization-with-usage-models

3. sysfy

https://chromium.googlesource.com/external/github.com/altera-opensource/linux-socfpga/+/refs/heads/master/Documentation/x86/intel_rdt_ui.txt

4. cache的科普文章，特别不错。

http://cenalulu.github.io/linux/all-about-cpu-cache/

http://www.mouseos.com/arch/cache.html

http://mil-embedded.com/articles/cache-utilization-safety-critical-multicore-applications/  cache partation

https://danluu.com/intel-cat/  intel introduce cache partation

https://www.findhao.net/easycoding/1694　introudce cache info in sys

5.  Cache Monitoring Technology tools

https://software.intel.com/en-us/blogs/2014/12/11/intels-cache-monitoring-technology-software-support-and-tools

https://software.intel.com/en-us/blogs/2014/06/18/benefit-of-cache-monitoring

https://software.intel.com/en-us/blogs/2014/12/11/intel-s-cache-monitoring-technology-software-visible-interfaces

 

6. tdt in kernel

https://lkml.org/lkml/2016/9/8/84  总结性文档

https://lkml.org/lkml/fancy/2016/9/8/70　task　reap zombie

https://lkml.org/lkml/fancy/2016/9/8/74 　核心，ｓｃｈｅｄｕｌｅ　ｓｕｐｐｏｒｔ

搞了一个软件ＭＳ　避免延时。

rdmsr latency for IA32_PQR_MSR is very high (~250
cycles) this software cache is necessary to avoid reading the MSR to
compare the current CLOSid value.

 - MSR write is only done when there is a task with different Closid is
scheduled on the CPU. Typically if the task groups are bound to be
scheduled on a set of CPUs, the number of MSR writes is greatly
reduced.

 

https://lkml.org/lkml/fancy/2016/9/8/81　　Hot cpu update for code data prioritization

 

7. cqm perf improvement in kernel

https://lkml.org/lkml/2017/1/6/814

https://lkml.org/lkml/2017/1/6/719 

Task associated wiht RMIDs.  u32 *rmid in the task_struck。

Task associated wiht it's cgroup.  a list in the arch_info of perf_cgroup called taskmon_list

https://lkml.org/lkml/2017/1/6/803  Scheduling support update

https://lkml.org/lkml/2017/1/6/808

 

8.  Using Hardware Features in Intel® Architecture to Achieve High Performance in NFV

RDT 应用：

https://software.intel.com/en-us/articles/using-hardware-features-in-intel-architecture-to-achieve-high-performance-in-nfv

 

9. monitor support in kernel.

https://lkml.org/lkml/2017/6/26/619

 

10. Cache Coherency

缓存一致性（Cache Coherency）入门

CAS原理之缓存一致性

CAS指令与MESI缓存一致性协议

 

转载于:https://www.cnblogs.com/shaohef/p/6636526.html