usb reset失败 linux,USB——usb host controller reset&start

hcd reset

在USB——usb host controller driver初始化一文中分析到，其初始化过程，在usb_add_hcd()函数中做了很多事情，会调用到hcd驱动的reset和start。本文对reset和start过程中会做什么事情进行分析。

reset

freescale芯片的reset函数代码如下

static int ehci_fsl_setup(struct usb_hcd *hcd)

{

struct ehci_hcd *ehci = hcd_to_ehci(hcd);

int retval;

/* EHCI registers start at offset 0x100 */

ehci->caps = hcd->regs + 0x100;

ehci->regs = hcd->regs + 0x100 +

HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));

dbg_hcs_params(ehci, "reset");

dbg_hcc_params(ehci, "reset");

/* cache this readonly data; minimize chip reads */

ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);

retval = ehci_halt(ehci);

if (retval)

return retval;

/* data structure init */

retval = ehci_init(hcd);

if (retval)

return retval;

hcd->has_tt = 1;

ehci->sbrn = 0x20;

ehci_reset(ehci);

retval = ehci_fsl_reinit(ehci);

return retval;

}

关于能力寄存器

第一件事情是读取主机控制器的hcs_params寄存器，在USB标准中规定了主机控制器必须有一些能力寄存器用以指示它的能力和限制(Host Controller Capability Registers)，以EHCI标准为例，这些寄存器如下表

代码中读取的是HCSPARAMS寄存器，该寄存器有以下几个部分较为重要

Port Indicators：表示端口是否支持指示灯控制

Number of Companion Controller：表示是否有伴随控制器

Number of Ports per Companion Controller：表示每个伴随控制器拥有几个端口

Port Routing Rules：表示端口和伴随控制器的映射关系

Port Power Control：表示是否支持端口功率控制

N_PORTS：表示物理端口数量

hcd halt

代码中将读取的内容保存在hcs_params中。然后调用了ehci_halt()，代码如下

static int ehci_halt (struct ehci_hcd *ehci)

{

u32temp = ehci_readl(ehci, &ehci->regs->status);

/* disable any irqs left enabled by previous code */

ehci_writel(ehci, 0, &ehci->regs->intr_enable);

if ((temp & STS_HALT) != 0)

return 0;

temp = ehci_readl(ehci, &ehci->regs->command);

temp &= ~CMD_RUN;

ehci_writel(ehci, temp, &ehci->regs->command);

return handshake (ehci, &ehci->regs->status,

STS_HALT, STS_HALT, 16 * 125);

}

首先读状态寄存器，然后向中断使能寄存其中写0关中断，如果状态已经是暂停了，就返回，如果不是暂停状态，向命令寄存其中写值使hcd进入暂停状态，最后调用的handshake()是循环一定的时间轮询状态寄存器，等待硬件变为暂停状态。

hcd init

将hcd暂停后，调用了ehci_init()，代码如下

static int ehci_init(struct usb_hcd *hcd)

{

struct ehci_hcd*ehci = hcd_to_ehci(hcd);

u32temp;

intretval;

u32hcc_params;

struct ehci_qh_hw*hw;

spin_lock_init(&ehci->lock);

/*

* keep io watchdog by default, those good HCDs could turn off it later

*/

ehci->need_io_watchdog = 1;

init_timer(&ehci->watchdog);

ehci->watchdog.function = ehci_watchdog;

ehci->watchdog.data = (unsigned long) ehci;

init_timer(&ehci->iaa_watchdog);

ehci->iaa_watchdog.function = ehci_iaa_watchdog;

ehci->iaa_watchdog.data = (unsigned long) ehci;

/*

* hw default: 1K periodic list heads, one per frame.

* periodic_size can shrink by USBCMD update if hcc_params allows.

*/

ehci->periodic_size = DEFAULT_I_TDPS;

INIT_LIST_HEAD(&ehci->cached_itd_list);

if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)

return retval;

/* controllers may cache some of the periodic schedule ... */

hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);

if (HCC_ISOC_CACHE(hcc_params))// full frame cache

ehci->i_thresh = 8;

else// N microframes cached

ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);

ehci->reclaim = NULL;

ehci->next_uframe = -1;

ehci->clock_frame = -1;

/*

* dedicate a qh for the async ring head, since we couldn't unlink

* a 'real' qh without stopping the async schedule [4.8]. use it

* as the 'reclamation list head' too.

* its dummy is used in hw_alt_next of many tds, to prevent the qh

* from automatically advancing to the next td after short reads.

*/

ehci->async->qh_next.qh = NULL;

hw = ehci->async->hw;

hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);

hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);

hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);

hw->hw_qtd_next = EHCI_LIST_END(ehci);

ehci->async->qh_state = QH_STATE_LINKED;

hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);

/* clear interrupt enables, set irq latency */

if (log2_irq_thresh < 0 || log2_irq_thresh > 6)

log2_irq_thresh = 0;

temp = 1 << (16 + log2_irq_thresh);

if (HCC_CANPARK(hcc_params)) {

/* HW default park == 3, on hardware that supports it (like

* NVidia and ALI silicon), maximizes throughput on the async

* schedule by avoiding QH fetches between transfers.

*

* With fast usb storage devices and NForce2, "park" seems to

* make problems: throughput reduction (!), data errors...

*/

if (park) {

park = min(park, (unsigned) 3);

temp |= CMD_PARK;

temp |= park << 8;

}

ehci_dbg(ehci, "park %d\n", park);

}

if (HCC_PGM_FRAMELISTLEN(hcc_params)) {

/* periodic schedule size can be smaller than default */

temp &= ~(3 << 2);

temp |= (EHCI_TUNE_FLS << 2);

switch (EHCI_TUNE_FLS) {

case 0: ehci->periodic_size = 1024; break;

case 1: ehci->periodic_size = 512; break;

case 2: ehci->periodic_size = 256; break;

default:BUG();

}

}

ehci->command = temp;

return 0;

}

首先初始化了两个定时任务ehci_watchdog()和ehci_iaa_watchdog()，来看看ehci_watchdog()函数

static void ehci_watchdog(unsigned long param)

{

struct ehci_hcd*ehci = (struct ehci_hcd *) param;

unsigned longflags;

spin_lock_irqsave(&ehci->lock, flags);

/* stop async processing after it's idled a bit */

if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))

start_unlink_async (ehci, ehci->async);

/* ehci could run by timer, without IRQs ... */

ehci_work (ehci);

spin_unlock_irqrestore (&ehci->lock, flags);

}

先测试actions中的TIMER_ASYNC_OFF是否被置位，字面意思就是是否当前没有进行异步操作，如果没有的话，就调用start_unlink_async()，然后调用了ehci_work()。看到这里，会感觉有些陌生，但是感觉work、async什么的应该很重要，对，这里涉及到USB中异步调度的问题，是硬件实现的，现在我们只要知道hcd的init过程，提前申请了一个定时器任务来处理异步调度的事情就可以了，然后在此后的过程中会因为什么契机被触发出来。详细的异步调度总结参见另一篇文章异步调度

另一个定时任务是ehci_iaa_watchdog()，代码如下

static void ehci_iaa_watchdog(unsigned long param)

{

struct ehci_hcd*ehci = (struct ehci_hcd *) param;

unsigned longflags;

spin_lock_irqsave (&ehci->lock, flags);

/* Lost IAA irqs wedge things badly; seen first with a vt8235.

* So we need this watchdog, but must protect it against both

* (a) SMP races against real IAA firing and retriggering, and

* (b) clean HC shutdown, when IAA watchdog was pending.

*/

if (ehci->reclaim

&& !timer_pending(&ehci->iaa_watchdog)

&& HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {

u32 cmd, status;

/* If we get here, IAA is *REALLY* late. It's barely

* conceivable that the system is so busy that CMD_IAAD

* is still legitimately set, so let's be sure it's

* clear before we read STS_IAA. (The HC should clear

* CMD_IAAD when it sets STS_IAA.)

*/

cmd = ehci_readl(ehci, &ehci->regs->command);

if (cmd & CMD_IAAD)

ehci_writel(ehci, cmd & ~CMD_IAAD,

&ehci->regs->command);

/* If IAA is set here it either legitimately triggered

* before we cleared IAAD above (but _way_ late, so we'll

* still count it as lost) ... or a silicon erratum:

* - VIA seems to set IAA without triggering the IRQ;

* - IAAD potentially cleared without setting IAA.

*/

status = ehci_readl(ehci, &ehci->regs->status);

if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {

COUNT (ehci->stats.lost_iaa);

ehci_writel(ehci, STS_IAA, &ehci->regs->status);

}

ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",

status, cmd);

end_unlink_async(ehci);

}

spin_unlock_irqrestore(&ehci->lock, flags);

}

这里涉及到两个重要的寄存器位，一个是命令寄存器中的Interrupt on Async Advance Doorbell，简称IAAD，它表示是否在hcd进行异步调度后发生中断，另一个是状态寄存器中的Interrupt on Async Advance，表示因为异步调度产生了中断。进行了一些逻辑判断后还是调用了一个看上去和异步相关的函数end_unlink_async()。不再继续分析了。

hcd mem init

申请完了两个定时任务后，调用了ehci_mem_init()，看看代码

static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)

{

int i;

/* QTDs for control/bulk/intr transfers */

ehci->qtd_pool = dma_pool_create ("ehci_qtd",

ehci_to_hcd(ehci)->self.controller,

sizeof (struct ehci_qtd),

32 /* byte alignment (for hw parts) */,

4096 /* can't cross 4K */);

if (!ehci->qtd_pool) {

goto fail;

}

/* QHs for control/bulk/intr transfers */

ehci->qh_pool = dma_pool_create ("ehci_qh",

ehci_to_hcd(ehci)->self.controller,

sizeof(struct ehci_qh_hw),

32 /* byte alignment (for hw parts) */,

4096 /* can't cross 4K */);

if (!ehci->qh_pool) {

goto fail;

}

ehci->async = ehci_qh_alloc (ehci, flags);

if (!ehci->async) {

goto fail;

}

/* ITD for high speed ISO transfers */

ehci->itd_pool = dma_pool_create ("ehci_itd",

ehci_to_hcd(ehci)->self.controller,

sizeof (struct ehci_itd),

32 /* byte alignment (for hw parts) */,

4096 /* can't cross 4K */);

if (!ehci->itd_pool) {

goto fail;

}

/* SITD for full/low speed split ISO transfers */

ehci->sitd_pool = dma_pool_create ("ehci_sitd",

ehci_to_hcd(ehci)->self.controller,

sizeof (struct ehci_sitd),

32 /* byte alignment (for hw parts) */,

4096 /* can't cross 4K */);

if (!ehci->sitd_pool) {

goto fail;

}

/* Hardware periodic table */

ehci->periodic = (__le32 *)

dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,

ehci->periodic_size * sizeof(__le32),

&ehci->periodic_dma, 0);

if (ehci->periodic == NULL) {

goto fail;

}

for (i = 0; i < ehci->periodic_size; i++)

ehci->periodic [i] = EHCI_LIST_END(ehci);

/* software shadow of hardware table */

ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);

if (ehci->pshadow != NULL)

return 0;

fail:

ehci_dbg (ehci, "couldn't init memory\n");

ehci_mem_cleanup (ehci);

return -ENOMEM;

}

调用4次dma_pool_create()，为hcd里的四个dma pool指针申请了dma pool，它们的大小分别为ehci_qtd、ehci_qh_hw、ehci_itd和ehci_sitd结构体的大小，这四个结构体也是USB标准规定的，是hcd硬件实现的数据结构，因此要使用dma将其映射到内存空间。USB传输方式有控制、中断、块和等时四种方式，qtd、qh用于控制、中断和块传输，itd和sitd用于等时传输，具体的结构体细节可参见EHCI标准文档

创建dma pool后，还调用了ehci_qh_alloc()函数，代码如下

static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)

{

struct ehci_qh*qh;

dma_addr_tdma;

qh = kzalloc(sizeof *qh, GFP_ATOMIC);

if (!qh)

goto done;

qh->hw = (struct ehci_qh_hw *)

dma_pool_alloc(ehci->qh_pool, flags, &dma);

if (!qh->hw)

goto fail;

memset(qh->hw, 0, sizeof *qh->hw);

qh->refcount = 1;

qh->ehci = ehci;

qh->qh_dma = dma;

// INIT_LIST_HEAD (&qh->qh_list);

INIT_LIST_HEAD (&qh->qtd_list);

/* dummy td enables safe urb queuing */

qh->dummy = ehci_qtd_alloc (ehci, flags);

if (qh->dummy == NULL) {

ehci_dbg (ehci, "no dummy td\n");

goto fail1;

}

done:

return qh;

fail1:

dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);

fail:

kfree(qh);

return NULL;

}

首先调用kmalloc()分配了一个ehci_qh空间，这个结构体是硬件无关的，用于记录和管理qh的dma地址和虚拟地址，调用dma_pool_alloc()从qh的dma pool中分配出内存空间，将虚拟地址和dma地址都记录在ehci_qh结构中。然后调用了ehci_qtd_alloc()函数，代码如下

static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)

{

struct ehci_qtd*qtd;

dma_addr_tdma;

qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);

if (qtd != NULL) {

ehci_qtd_init(ehci, qtd, dma);

}

return qtd;

}

从qtd的dma pool中分配了内存空间，虚拟地址返回，用qh的dummy指针指向这个内存空间，然后调用ehci_qtd_init()对qtd进行初始化，

static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,

dma_addr_t dma)

{

memset (qtd, 0, sizeof *qtd);

qtd->qtd_dma = dma;

qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);

qtd->hw_next = EHCI_LIST_END(ehci);

qtd->hw_alt_next = EHCI_LIST_END(ehci);

INIT_LIST_HEAD (&qtd->qtd_list);

}

在其中将qtd的dma地址记录下来。

返回到ehci_mem_init()函数，最后调用dma_alloc_coherent()为periodic分配了一致性dma空间，一共有32个periodic，每一个1k，总共32k，循环每一个periodic进行了初始化赋值。periodic也是USB标准中的规定数据结构。

总结ehci_mem_init()函数，主要做了以下事情

创建了4个dma pool，分别与硬件的qtd、qh、itd、istd对应

分配ehci_qh结构体用于管理qh和qtd的dma内存地址，qh为1级，qtd为2级，ehci_hcd的async指针指向分配的ehci_qh结构体，ehci_qh结构体的两个地址hw和qh_dma指针分别指向由qh dma pool分配出来dma空间的虚拟地址和物理地址，dummy指向分配的ehci_qtd结构体，ehci_qtd结构体指针指向qtd dma pool分配的虚拟地址，qtd_dma成员指针指向其物理地址

为periodic分配一致性dma空间并初始化

内存分配涉及的结构体、指针以及dma操作比较复杂，用下图来总结

hcd reset

mem初始化完成后，调用了ehci_reset()函数，代码如下

static int ehci_reset (struct ehci_hcd *ehci)

{

intretval;

u32command = ehci_readl(ehci, &ehci->regs->command);

/* If the EHCI debug controller is active, special care must be

* taken before and after a host controller reset */

if (ehci->debug && !dbgp_reset_prep())

ehci->debug = NULL;

command |= CMD_RESET;

dbg_cmd (ehci, "reset", command);

ehci_writel(ehci, command, &ehci->regs->command);

ehci_to_hcd(ehci)->state = HC_STATE_HALT;

ehci->next_statechange = jiffies;

retval = handshake (ehci, &ehci->regs->command,

CMD_RESET, 0, 250 * 1000);

if (ehci->has_hostpc) {

ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,

(u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));

ehci_writel(ehci, TXFIFO_DEFAULT,

(u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));

}

if (retval)

return retval;

if (ehci_is_TDI(ehci))

tdi_reset (ehci);

if (ehci->debug)

dbgp_external_startup();

return retval;

}

主要就是对命令寄存器写RESET命令，使硬件reset。

下一步调用ehci_fsl_reinit()，代码

static int ehci_fsl_reinit(struct ehci_hcd *ehci)

{

mpc83xx_usb_setup(ehci_to_hcd(ehci));

ehci_port_power(ehci, 0);

return 0;

}

第一个函数mpc83xx_usb_setup()进行USB的PHY初始化，第二个函数ehci_port_power()通过ehci_hub_control()对每个端口的状态寄存器进行设置，使能所有端口。

start

hcd的启动函数是ehci_run()，代码如下

static int ehci_run (struct usb_hcd *hcd)

{

struct ehci_hcd*ehci = hcd_to_ehci (hcd);

intretval;

u32temp;

u32hcc_params;

hcd->uses_new_polling = 1;

hcd->poll_rh = 0;

/* EHCI spec section 4.1 */

if ((retval = ehci_reset(ehci)) != 0) {

ehci_mem_cleanup(ehci);

return retval;

}

ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);

ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);

/*

* hcc_params controls whether ehci->regs->segment must (!!!)

* be used; it constrains QH/ITD/SITD and QTD locations.

* pci_pool consistent memory always uses segment zero.

* streaming mappings for I/O buffers, like pci_map_single(),

* can return segments above 4GB, if the device allows.

*

* NOTE: the dma mask is visible through dma_supported(), so

* drivers can pass this info along ... like NETIF_F_HIGHDMA,

* Scsi_Host.highmem_io, and so forth. It's readonly to all

* host side drivers though.

*/

hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);

if (HCC_64BIT_ADDR(hcc_params)) {

ehci_writel(ehci, 0, &ehci->regs->segment);

#if 0

// this is deeply broken on almost all architectures

if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))

ehci_info(ehci, "enabled 64bit DMA\n");

#endif

}

// Philips, Intel, and maybe others need CMD_RUN before the

// root hub will detect new devices (why?); NEC doesn't

ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);

ehci->command |= CMD_RUN;

ehci_writel(ehci, ehci->command, &ehci->regs->command);

dbg_cmd (ehci, "init", ehci->command);

/*

* Start, enabling full USB 2.0 functionality ... usb 1.1 devices

* are explicitly handed to companion controller(s), so no TT is

* involved with the root hub. (Except where one is integrated,

* and there's no companion controller unless maybe for USB OTG.)

*

* Turning on the CF flag will transfer ownership of all ports

* from the companions to the EHCI controller. If any of the

* companions are in the middle of a port reset at the time, it

* could cause trouble. Write-locking ehci_cf_port_reset_rwsem

* guarantees that no resets are in progress. After we set CF,

* a short delay lets the hardware catch up; new resets shouldn't

* be started before the port switching actions could complete.

*/

down_write(&ehci_cf_port_reset_rwsem);

hcd->state = HC_STATE_RUNNING;

ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);

ehci_readl(ehci, &ehci->regs->command);/* unblock posted writes */

msleep(5);

up_write(&ehci_cf_port_reset_rwsem);

ehci->last_periodic_enable = ktime_get_real();

temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));

ehci_info (ehci,

"USB %x.%x started, EHCI %x.%02x%s\n",

((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),

temp >> 8, temp & 0xff,

ignore_oc ? ", overcurrent ignored" : "");

ehci_writel(ehci, INTR_MASK,

&ehci->regs->intr_enable); /* Turn On Interrupts */

/* GRR this is run-once init(), being done every time the HC starts.

* So long as they're part of class devices, we can't do it init()

* since the class device isn't created that early.

*/

create_debug_files(ehci);

create_companion_file(ehci);

return 0;

}

首先是调用ehci_reset()，这是第二次reset了。下一步的操作很重要，设置了两个寄存器的值，一个是frame_list，另一个是async_next。frame_list寄存器是Periodic Frame List Base Address Register，周期性帧列表基址寄存器，这个寄存器指向系统中分配的periodic

区域，指向哪里呢，就是mem初始化中创建的32k Periodic 区域。

async_next是Next Asynchronous List Addr，即下一个异步列表地址寄存器。

然后清命令寄存器，向命令寄存器中写RUN命令，启动主机控制器工作，向中断使能寄存器中写入掩码使能异步调度中断、错误中断、端口状态检测中断