Abstract
DE2可外接CCD和彩色LCD，如此可實作出簡單的數位相機，本篇先介紹使用Verilog純硬體的方式讓CCD影像顯示在彩色 LCD上。
使用環境：Quartus II 7.2 SP1 + Nios II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6) + TRDB_LCM + TRDB_DC2
Introduction
DE2除了有豐富的周邊外，還可外接130萬像素的CCD和3.6吋的LCM(LCD Control Module)，搭配這兩個外接模組，便可實作簡單的數位相機。
Fig.1 外接130萬像素CCD模組
Fig.2 3.6吋彩色LCD
Fig.3 DE2和CCD與LCD合體後。
功能介紹
KEY[0]為reset鍵，用來重設整個系統。
KEY[1]可設定曝光值。
KEY[3]進入待機模式，此時CCD影像將顯示在LCD上。
KEY[2]可進行拍照功能，此時LCD會顯示所拍到的影像。
SW[15:0]可設定曝光值。一般而言，在室內的曝光值設定，僅需將SW[9]和SW[10]設為ON即可，可自行根據環境亮度設定合適的曝光值。
系統方塊圖
CCD部分是以I2C方式控制，由I2C產生CCD module所需的時脈，而CCD Data Capture產生第一個module所需的clock。當資料擷取後，所擷取的資料為RAW格式，須將此格式轉換為RGB格式才能顯示在LCD上。
轉換後的資料經由SDRAM Controller存入SDRAM，此為Multi-Port輸入，因此資料會不停地依序輸入與輸出。
在LCD module控制上，採用的是I2S控制驅動，並將所轉換的像素由列至行依序排列至LCD面板上。
Verilog
以下程式碼為友晶科技所提供，我並沒有將所有的module都列出，僅列出最關鍵的module。若需要完整的程式碼，可至友晶科技網站下載：DE2_LCM_CCD.zip，或者下載我上傳的版本：DE2_LCM_CCD.7z。
DE2_LCM_CCD.v
整個專案的top module，負責聯繫所有module。
1
module DE2_LCM_CCD (
2 / / Clock Input // //
3 CLOCK_27, // 27 MHz
4 CLOCK_50, // 50 MHz
5 EXT_CLOCK, // External Clock
6 / / Push Button // //
7 KEY, // Pushbutton[3:0]
8 // // DPDT Switch // //
9 SW, // Toggle Switch[17:0]
10 / / 7-SEG Dispaly // //
11 HEX0, // Seven Segment Digit 0
12 HEX1, // Seven Segment Digit 1
13 HEX2, // Seven Segment Digit 2
14 HEX3, // Seven Segment Digit 3
15 HEX4, // Seven Segment Digit 4
16 HEX5, // Seven Segment Digit 5
17 HEX6, // Seven Segment Digit 6
18 HEX7, // Seven Segment Digit 7
19 / / LED
20 LEDG, // LED Green[8:0]
21 LEDR, // LED Red[17:0]
22 / / UART
23 UART_TXD, // UART Transmitter
24 UART_RXD, // UART Receiver
25 / / IRDA
26 IRDA_TXD, // IRDA Transmitter
27 IRDA_RXD, // IRDA Receiver
28 / / SDRAM Interface /// /
29 DRAM_DQ, // SDRAM Data bus 16 Bits
30 DRAM_ADDR, // SDRAM Address bus 12 Bits
31 DRAM_LDQM, // SDRAM Low-byte Data Mask
32 DRAM_UDQM, // SDRAM High-byte Data Mask
33 DRAM_WE_N, // SDRAM Write Enable
34 DRAM_CAS_N, // SDRAM Column Address Strobe
35 DRAM_RAS_N, // SDRAM Row Address Strobe
36 DRAM_CS_N, // SDRAM Chip Select
37 DRAM_BA_0, // SDRAM Bank Address 0
38 DRAM_BA_1, // SDRAM Bank Address 0
39 DRAM_CLK, // SDRAM Clock
40 DRAM_CKE, // SDRAM Clock Enable
41 / / Flash Interface /// /
42 FL_DQ, // FLASH Data bus 8 Bits
43 FL_ADDR, // FLASH Address bus 22 Bits
44 FL_WE_N, // FLASH Write Enable
45 FL_RST_N, // FLASH Reset
46 FL_OE_N, // FLASH Output Enable
47 FL_CE_N, // FLASH Chip Enable
48 / / SRAM Interface /// /
49 SRAM_DQ, // SRAM Data bus 16 Bits
50 SRAM_ADDR, // SRAM Address bus 18 Bits
51 SRAM_UB_N, // SRAM High-byte Data Mask
52 SRAM_LB_N, // SRAM Low-byte Data Mask
53 SRAM_WE_N, // SRAM Write Enable
54 SRAM_CE_N, // SRAM Chip Enable
55 SRAM_OE_N, // SRAM Output Enable
56 / / ISP1362 Interface /// /
57 OTG_DATA, // ISP1362 Data bus 16 Bits
58 OTG_ADDR, // ISP1362 Address 2 Bits
59 OTG_CS_N, // ISP1362 Chip Select
60 OTG_RD_N, // ISP1362 Write
61 OTG_WR_N, // ISP1362 Read
62 OTG_RST_N, // ISP1362 Reset
63 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
64 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
65 OTG_INT0, // ISP1362 Interrupt 0
66 OTG_INT1, // ISP1362 Interrupt 1
67 OTG_DREQ0, // ISP1362 DMA Request 0
68 OTG_DREQ1, // ISP1362 DMA Request 1
69 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
70 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
71 / / LCD Module 16X2 /// /
72 LCD_ON, // LCD Power ON/OFF
73 LCD_BLON, // LCD Back Light ON/OFF
74 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
75 LCD_EN, // LCD Enable
76 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
77 LCD_DATA, // LCD Data bus 8 bits
78 / / SD_Card Interface /// /
79 SD_DAT, // SD Card Data
80 SD_DAT3, // SD Card Data 3
81 SD_CMD, // SD Card Command Signal
82 SD_CLK, // SD Card Clock
83 / / USB JTAG link // //
84 TDI, // CPLD -> FPGA (data in)
85 TCK, // CPLD -> FPGA (clk)
86 TCS, // CPLD -> FPGA (CS)
87 TDO, // FPGA -> CPLD (data out)
88 / / I2C /// /
89 I2C_SDAT, // I2C Data
90 I2C_SCLK, // I2C Clock
91 / / PS2 /// /
92 PS2_DAT, // PS2 Data
93 PS2_CLK, // PS2 Clock
94 / / VGA /// /
95 VGA_CLK, // VGA Clock
96 VGA_HS, // VGA H_SYNC
97 VGA_VS, // VGA V_SYNC
98 VGA_BLANK, // VGA BLANK
99 VGA_SYNC, // VGA SYNC
100 VGA_R, // VGA Red[9:0]
101 VGA_G, // VGA Green[9:0]
102 VGA_B, // VGA Blue[9:0]
103 / / Ethernet Interface
104 ENET_DATA, // DM9000A DATA bus 16Bits
105 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
106 ENET_CS_N, // DM9000A Chip Select
107 ENET_WR_N, // DM9000A Write
108 ENET_RD_N, // DM9000A Read
109 ENET_RST_N, // DM9000A Reset
110 ENET_INT, // DM9000A Interrupt
111 ENET_CLK, // DM9000A Clock 25 MHz
112 / / Audio CODEC
113 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
114 AUD_ADCDAT, // Audio CODEC ADC Data
115 AUD_DACLRCK, // Audio CODEC DAC LR Clock
116 AUD_DACDAT, // Audio CODEC DAC Data
117 AUD_BCLK, // Audio CODEC Bit-Stream Clock
118 AUD_XCK, // Audio CODEC Chip Clock
119 / / TV Decoder
120 TD_DATA, // TV Decoder Data bus 8 bits
121 TD_HS, // TV Decoder H_SYNC
122 TD_VS, // TV Decoder V_SYNC
123 TD_RESET, // TV Decoder Reset
124 / / GPIO /// /
125 GPIO_0, // GPIO Connection 0
126 GPIO_1 // GPIO Connection 1
127 );
128
129 // Clock Input
130 input CLOCK_27; // 27 MHz
131 input CLOCK_50; // 50 MHz
132 input EXT_CLOCK; // External Clock
133 // Push Button
134 input [ 3 : 0 ] KEY; // Pushbutton[3:0]
135 // DPDT Switch
136 input [ 17 : 0 ] SW; // Toggle Switch[17:0]
137 // 7-SEG Dispaly
138 output [ 6 : 0 ] HEX0; // Seven Segment Digit 0
139 output [ 6 : 0 ] HEX1; // Seven Segment Digit 1
140 output [ 6 : 0 ] HEX2; // Seven Segment Digit 2
141 output [ 6 : 0 ] HEX3; // Seven Segment Digit 3
142 output [ 6 : 0 ] HEX4; // Seven Segment Digit 4
143 output [ 6 : 0 ] HEX5; // Seven Segment Digit 5
144 output [ 6 : 0 ] HEX6; // Seven Segment Digit 6
145 output [ 6 : 0 ] HEX7; // Seven Segment Digit 7
146 // LED /// /
147 output [ 8 : 0 ] LEDG; // LED Green[8:0]
148 output [ 17 : 0 ] LEDR; // LED Red[17:0]
149 // UART /// /
150 output UART_TXD; // UART Transmitter
151 input UART_RXD; // UART Receiver
152 // IRDA /// /
153 output IRDA_TXD; // IRDA Transmitter
154 input IRDA_RXD; // IRDA Receiver
155 // SDRAM Interface
156 inout [ 15 : 0 ] DRAM_DQ; // SDRAM Data bus 16 Bits
157 output [ 11 : 0 ] DRAM_ADDR; // SDRAM Address bus 12 Bits
158 output DRAM_LDQM; // SDRAM Low-byte Data Mask
159 output DRAM_UDQM; // SDRAM High-byte Data Mask
160 output DRAM_WE_N; // SDRAM Write Enable
161 output DRAM_CAS_N; // SDRAM Column Address Strobe
162 output DRAM_RAS_N; // SDRAM Row Address Strobe
163 output DRAM_CS_N; // SDRAM Chip Select
164 output DRAM_BA_0; // SDRAM Bank Address 0
165 output DRAM_BA_1; // SDRAM Bank Address 0
166 output DRAM_CLK; // SDRAM Clock
167 output DRAM_CKE; // SDRAM Clock Enable
168 // Flash Interface
169 inout [ 7 : 0 ] FL_DQ; // FLASH Data bus 8 Bits
170 output [ 21 : 0 ] FL_ADDR; // FLASH Address bus 22 Bits
171 output FL_WE_N; // FLASH Write Enable
172 output FL_RST_N; // FLASH Reset
173 output FL_OE_N; // FLASH Output Enable
174 output FL_CE_N; // FLASH Chip Enable
175 // SRAM Interface
176 inout [ 15 : 0 ] SRAM_DQ; // SRAM Data bus 16 Bits
177 output [ 17 : 0 ] SRAM_ADDR; // SRAM Address bus 18 Bits
178 output SRAM_UB_N; // SRAM High-byte Data Mask
179 output SRAM_LB_N; // SRAM Low-byte Data Mask
180 output SRAM_WE_N; // SRAM Write Enable
181 output SRAM_CE_N; // SRAM Chip Enable
182 output SRAM_OE_N; // SRAM Output Enable
183 // ISP1362 Interface
184 inout [ 15 : 0 ] OTG_DATA; // ISP1362 Data bus 16 Bits
185 output [ 1 : 0 ] OTG_ADDR; // ISP1362 Address 2 Bits
186 output OTG_CS_N; // ISP1362 Chip Select
187 output OTG_RD_N; // ISP1362 Write
188 output OTG_WR_N; // ISP1362 Read
189 output OTG_RST_N; // ISP1362 Reset
190 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
191 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
192 input OTG_INT0; // ISP1362 Interrupt 0
193 input OTG_INT1; // ISP1362 Interrupt 1
194 input OTG_DREQ0; // ISP1362 DMA Request 0
195 input OTG_DREQ1; // ISP1362 DMA Request 1
196 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
197 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
198 // LCD Module 16X2 /// /
199 inout [ 7 : 0 ] LCD_DATA; // LCD Data bus 8 bits
200 output LCD_ON; // LCD Power ON/OFF
201 output LCD_BLON; // LCD Back Light ON/OFF
202 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
203 output LCD_EN; // LCD Enable
204 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
205 // SD Card Interface
206 inout SD_DAT; // SD Card Data
207 inout SD_DAT3; // SD Card Data 3
208 inout SD_CMD; // SD Card Command Signal
209 output SD_CLK; // SD Card Clock
210 // I2C // //
211 inout I2C_SDAT; // I2C Data
212 output I2C_SCLK; // I2C Clock
213 // PS2 // //
214 input PS2_DAT; // PS2 Data
215 input PS2_CLK; // PS2 Clock
216 // USB JTAG link /// /
217 input TDI; // CPLD -> FPGA (data in)
218 input TCK; // CPLD -> FPGA (clk)
219 input TCS; // CPLD -> FPGA (CS)
220 output TDO; // FPGA -> CPLD (data out)
221 // VGA /// /
222 output VGA_CLK; // VGA Clock
223 output VGA_HS; // VGA H_SYNC
224 output VGA_VS; // VGA V_SYNC
225 output VGA_BLANK; // VGA BLANK
226 output VGA_SYNC; // VGA SYNC
227 output [ 9 : 0 ] VGA_R; // VGA Red[9:0]
228 output [ 9 : 0 ] VGA_G; // VGA Green[9:0]
229 output [ 9 : 0 ] VGA_B; // VGA Blue[9:0]
230 // Ethernet Interface /// /
231 inout [ 15 : 0 ] ENET_DATA; // DM9000A DATA bus 16Bits
232 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
233 output ENET_CS_N; // DM9000A Chip Select
234 output ENET_WR_N; // DM9000A Write
235 output ENET_RD_N; // DM9000A Read
236 output ENET_RST_N; // DM9000A Reset
237 input ENET_INT; // DM9000A Interrupt
238 output ENET_CLK; // DM9000A Clock 25 MHz
239 // Audio CODEC /// /
240 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
241 input AUD_ADCDAT; // Audio CODEC ADC Data
242 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
243 output AUD_DACDAT; // Audio CODEC DAC Data
244 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
245 output AUD_XCK; // Audio CODEC Chip Clock
246 // TV Devoder /// /
247 input [ 7 : 0 ] TD_DATA; // TV Decoder Data bus 8 bits
248 input TD_HS; // TV Decoder H_SYNC
249 input TD_VS; // TV Decoder V_SYNC
250 output TD_RESET; // TV Decoder Reset
251 // GPIO // //
252 inout [ 35 : 0 ] GPIO_0; // GPIO Connection 0
253 inout [ 35 : 0 ] GPIO_1; // GPIO Connection 1
254
255 // Turn on all display
256 assign LCD_ON = 1 ' b1;
257 assign LCD_BLON = 1 ' b1;
258
259 // All inout port turn to tri-state
260 assign DRAM_DQ = 16 ' hzzzz;
261 assign FL_DQ = 8 ' hzz;
262 assign SRAM_DQ = 16 ' hzzzz;
263 assign OTG_DATA = 16 ' hzzzz;
264 assign LCD_DATA = 8 ' hzz;
265 assign SD_DAT = 1 ' bz;
266 assign ENET_DATA = 16 ' hzzzz;
267 assign AUD_ADCLRCK = 1 ' bz;
268 assign AUD_DACLRCK = 1 ' bz;
269 assign AUD_BCLK = 1 ' bz;
270 assign TD_RESET = 1 ' b1;
271
272 For TFT LCD Module / //
273 wire [ 7 : 0 ] LCM_DATA; // LCM Data 8 Bits
274 wire LCM_GRST; // LCM Global Reset
275 wire LCM_SHDB; // LCM Sleep Mode
276 wire LCM_DCLK; // LCM Clcok
277 wire LCM_HSYNC; // LCM HSYNC
278 wire LCM_VSYNC; // LCM VSYNC
279 wire LCM_SCLK; // LCM I2C Clock
280 wire LCM_SDAT; // LCM I2C Data
281 wire LCM_SCEN; // LCM I2C Enable
282 wire CLK_18;
283
284 assign GPIO_0[ 18 ] = LCM_DATA[ 6 ];
285 assign GPIO_0[ 19 ] = LCM_DATA[ 7 ];
286 assign GPIO_0[ 20 ] = LCM_DATA[ 4 ];
287 assign GPIO_0[ 21 ] = LCM_DATA[ 5 ];
288 assign GPIO_0[ 22 ] = LCM_DATA[ 2 ];
289 assign GPIO_0[ 23 ] = LCM_DATA[ 3 ];
290 assign GPIO_0[ 24 ] = LCM_DATA[ 0 ];
291 assign GPIO_0[ 25 ] = LCM_DATA[ 1 ];
292 assign GPIO_0[ 26 ] = LCM_VSYNC;
293 assign GPIO_0[ 28 ] = LCM_SCLK;
294 assign GPIO_0[ 29 ] = LCM_DCLK;
295 assign GPIO_0[ 30 ] = LCM_GRST;
296 assign GPIO_0[ 31 ] = LCM_SHDB;
297 assign GPIO_0[ 33 ] = LCM_SCEN;
298 assign GPIO_0[ 34 ] = LCM_SDAT;
299 assign GPIO_0[ 35 ] = LCM_HSYNC;
300
301 For CMOS Sensor 1 / //
302 wire [ 9 : 0 ] CCD_DATA;
303 wire CCD_SDAT;
304 wire CCD_SCLK;
305 wire CCD_FLASH;
306 wire CCD_FVAL;
307 wire CCD_LVAL;
308 wire CCD_PIXCLK;
309 reg CCD_MCLK; // CCD Master Clock
310
311 wire [ 15 : 0 ] Read_DATA1;
312 wire [ 15 : 0 ] Read_DATA2;
313 wire [ 9 : 0 ] mCCD_DATA;
314 wire mCCD_DVAL;
315 wire mCCD_DVAL_d;
316 wire [ 10 : 0 ] X_Cont;
317 wire [ 10 : 0 ] Y_Cont;
318 wire [ 9 : 0 ] X_ADDR;
319 wire [ 31 : 0 ] Frame_Cont;
320 wire [ 9 : 0 ] mCCD_R;
321 wire [ 9 : 0 ] mCCD_G;
322 wire [ 9 : 0 ] mCCD_B;
323 wire DLY_RST_0;
324 wire DLY_RST_1;
325 wire DLY_RST_2;
326 wire Read;
327 reg [ 9 : 0 ] rCCD_DATA;
328 reg rCCD_LVAL;
329 reg rCCD_FVAL;
330 wire [ 9 : 0 ] sCCD_R;
331 wire [ 9 : 0 ] sCCD_G;
332 wire [ 9 : 0 ] sCCD_B;
333 wire sCCD_DVAL;
334
335 assign CCD_DATA[ 0 ] = GPIO_1[ 0 ];
336 assign CCD_DATA[ 1 ] = GPIO_1[ 1 ];
337 assign CCD_DATA[ 2 ] = GPIO_1[ 5 ];
338 assign CCD_DATA[ 3 ] = GPIO_1[ 3 ];
339 assign CCD_DATA[ 4 ] = GPIO_1[ 2 ];
340 assign CCD_DATA[ 5 ] = GPIO_1[ 4 ];
341 assign CCD_DATA[ 6 ] = GPIO_1[ 6 ];
342 assign CCD_DATA[ 7 ] = GPIO_1[ 7 ];
343 assign CCD_DATA[ 8 ] = GPIO_1[ 8 ];
344 assign CCD_DATA[ 9 ] = GPIO_1[ 9 ];
345 assign GPIO_1[ 11 ] = CCD_MCLK;
346 assign GPIO_1[ 15 ] = CCD_SDAT;
347 assign GPIO_1[ 14 ] = CCD_SCLK;
348 assign CCD_FVAL = GPIO_1[ 13 ];
349 assign CCD_LVAL = GPIO_1[ 12 ];
350 assign CCD_PIXCLK = GPIO_1[ 10 ];
351
352 assign LEDR = SW;
353 assign LEDG = Y_Cont;
354
355 always@(posedge CLOCK_50)
356 CCD_MCLK <= ~ CCD_MCLK;
357
358 always@(posedge CCD_PIXCLK)
359 begin
360 rCCD_DATA <= CCD_DATA;
361 rCCD_LVAL <= CCD_LVAL;
362 rCCD_FVAL <= CCD_FVAL;
363 end
364
365 LCM_PLL u0 (
366 .inclk0(CLOCK_27),
367 .c0(CLK_18)
368 );
369
370 LCM_Controller u1 (
371 // Host Side
372 .iRed(Read_DATA2[ 9 : 2 ]),
373 .iGreen({Read_DATA1[ 14 : 10 ], Read_DATA2[ 14 : 12 ]}),
374 .iBlue(Read_DATA1[ 9 : 2 ]),
375 // LCM Side
376 .LCM_DATA(LCM_DATA),
377 .LCM_VSYNC(LCM_VSYNC),
378 .LCM_HSYNC(LCM_HSYNC),
379 .LCM_DCLK(LCM_DCLK),
380 .LCM_SHDB(LCM_SHDB),
381 .LCM_GRST(LCM_GRST),
382 // Control Signals
383 .oDATA_REQ(Read),
384 .iCLK(CLK_18),
385 .iRST_N(DLY_RST_2)
386 );
387
388 Reset_Delay u2 (
389 .iCLK(CLOCK_50),
390 .iRST(KEY[ 0 ]),
391 .oRST_0(DLY_RST_0),
392 .oRST_1(DLY_RST_1),
393 .oRST_2(DLY_RST_2)
394 );
395
396 CCD_Capture u3 (
397 .oDATA(mCCD_DATA),
398 .oDVAL(mCCD_DVAL),
399 .oX_Cont(X_Cont),
400 .oY_Cont(Y_Cont),
401 .oFrame_Cont(Frame_Cont),
402 .iDATA(rCCD_DATA),
403 .iFVAL(rCCD_FVAL),
404 .iLVAL(rCCD_LVAL),
405 .iSTART( ! KEY[ 3 ]),
406 .iEND( ! KEY[ 2 ]),
407 .iCLK(CCD_PIXCLK),
408 .iRST(DLY_RST_1)
409 );
410
411 RAW2RGB u4 (
412 .oRed(mCCD_R),
413 .oGreen(mCCD_G),
414 .oBlue(mCCD_B),
415 .oDVAL(mCCD_DVAL_d),
416 .iX_Cont(X_Cont),
417 .iY_Cont(Y_Cont),
418 .iDATA(mCCD_DATA),
419 .iDVAL(mCCD_DVAL),
420 .iCLK(CCD_PIXCLK),
421 .iRST(DLY_RST_1)
422 );
423
424 SEG7_LUT_8 u5 (
425 .oSEG0(HEX0),
426 .oSEG1(HEX1),
427 .oSEG2(HEX2),
428 .oSEG3(HEX3),
429 .oSEG4(HEX4),
430 .oSEG5(HEX5),
431 .oSEG6(HEX6),
432 .oSEG7(HEX7),
433 .iDIG(Frame_Cont)
434 );
435
436 Sdram_Control_4Port u6 (
437 // HOST Side
438 .REF_CLK(CLOCK_50),
439 .RESET_N( 1 ' b1),
440 // FIFO Write Side 1
441 .WR1_DATA({sCCD_G[ 9 : 5 ], sCCD_B[ 9 : 0 ]}),
442 .WR1(sCCD_DVAL),
443 .WR1_ADDR( 0 ),
444 .WR1_MAX_ADDR( 320 * 256 ),
445 .WR1_LENGTH( 9 ' h100),
446 .WR1_LOAD( ! DLY_RST_0),
447 .WR1_CLK(CCD_PIXCLK),
448 // FIFO Write Side 2
449 .WR2_DATA({sCCD_G[ 4 : 0 ], sCCD_R[ 9 : 0 ]}),
450 .WR2(sCCD_DVAL),
451 .WR2_ADDR( 22 ' h100000),
452 .WR2_MAX_ADDR( 22 ' h100000+320*256),
453 .WR2_LENGTH( 9 ' h100),
454 .WR2_LOAD( ! DLY_RST_0),
455 .WR2_CLK(CCD_PIXCLK),
456 // FIFO Read Side 1
457 .RD1_DATA(Read_DATA1),
458 .RD1(Read),
459 .RD1_ADDR( 320 * 8 ),
460 .RD1_MAX_ADDR( 320 * 248 ),
461 .RD1_LENGTH( 9 ' h100),
462 .RD1_LOAD( ! DLY_RST_0),
463 .RD1_CLK(CLK_18),
464 // FIFO Read Side 2
465 .RD2_DATA(Read_DATA2),
466 .RD2(Read),
467 .RD2_ADDR( 22 ' h100000+320*8),
468 .RD2_MAX_ADDR( 22 ' h100000+320*248),
469 .RD2_LENGTH( 9 ' h100),
470 .RD2_LOAD( ! DLY_RST_0),
471 .RD2_CLK(CLK_18),
472 // SDRAM Side
473 .SA(DRAM_ADDR),
474 .BA({DRAM_BA_1,DRAM_BA_0}),
475 .CS_N(DRAM_CS_N),
476 .CKE(DRAM_CKE),
477 .RAS_N(DRAM_RAS_N),
478 .CAS_N(DRAM_CAS_N),
479 .WE_N(DRAM_WE_N),
480 .DQ(DRAM_DQ),
481 .DQM({DRAM_UDQM,DRAM_LDQM}),
482 .SDR_CLK(DRAM_CLK)
483 );
484
485 I2C_CCD_Config u7 (
486 // Host Side
487 .iCLK(CLOCK_50),
488 .iRST_N(KEY[ 1 ]),
489 .iExposure(SW[ 15 : 0 ]),
490 // I2C Side
491 .I2C_SCLK(CCD_SCLK),
492 .I2C_SDAT(CCD_SDAT)
493 );
494
495 I2S_LCM_Config u8 (
496 // Host Side
497 .iCLK(CLOCK_50),
498 .iRST_N(KEY[ 0 ]),
499 // I2C Side
500 .I2S_SCLK(LCM_SCLK),
501 .I2S_SDAT(LCM_SDAT),
502 .I2S_SCEN(LCM_SCEN)
503 );
504
505 I2C_AV_Config u9 (
506 // Host Side
507 .iCLK(CLOCK_50),
508 .iRST_N(KEY[ 0 ]),
509 // I2C Side
510 .I2C_SCLK(I2C_SCLK),
511 .I2C_SDAT(I2C_SDAT)
512 );
513
514 Mirror_Col u10 (
515 // Input Side
516 .iCCD_R(mCCD_R),
517 .iCCD_G(mCCD_G),
518 .iCCD_B(mCCD_B),
519 .iCCD_DVAL(mCCD_DVAL_d),
520 .iCCD_PIXCLK(CCD_PIXCLK),
521 .iRST_N(DLY_RST_1),
522 // Output Side
523 .oCCD_R(sCCD_R),
524 .oCCD_G(sCCD_G),
525 .oCCD_B(sCCD_B),
526 .oCCD_DVAL(sCCD_DVAL)
527 );
528
529 endmodule
2 / / Clock Input // //
3 CLOCK_27, // 27 MHz
4 CLOCK_50, // 50 MHz
5 EXT_CLOCK, // External Clock
6 / / Push Button // //
7 KEY, // Pushbutton[3:0]
8 // // DPDT Switch // //
9 SW, // Toggle Switch[17:0]
10 / / 7-SEG Dispaly // //
11 HEX0, // Seven Segment Digit 0
12 HEX1, // Seven Segment Digit 1
13 HEX2, // Seven Segment Digit 2
14 HEX3, // Seven Segment Digit 3
15 HEX4, // Seven Segment Digit 4
16 HEX5, // Seven Segment Digit 5
17 HEX6, // Seven Segment Digit 6
18 HEX7, // Seven Segment Digit 7
19 / / LED
20 LEDG, // LED Green[8:0]
21 LEDR, // LED Red[17:0]
22 / / UART
23 UART_TXD, // UART Transmitter
24 UART_RXD, // UART Receiver
25 / / IRDA
26 IRDA_TXD, // IRDA Transmitter
27 IRDA_RXD, // IRDA Receiver
28 / / SDRAM Interface /// /
29 DRAM_DQ, // SDRAM Data bus 16 Bits
30 DRAM_ADDR, // SDRAM Address bus 12 Bits
31 DRAM_LDQM, // SDRAM Low-byte Data Mask
32 DRAM_UDQM, // SDRAM High-byte Data Mask
33 DRAM_WE_N, // SDRAM Write Enable
34 DRAM_CAS_N, // SDRAM Column Address Strobe
35 DRAM_RAS_N, // SDRAM Row Address Strobe
36 DRAM_CS_N, // SDRAM Chip Select
37 DRAM_BA_0, // SDRAM Bank Address 0
38 DRAM_BA_1, // SDRAM Bank Address 0
39 DRAM_CLK, // SDRAM Clock
40 DRAM_CKE, // SDRAM Clock Enable
41 / / Flash Interface /// /
42 FL_DQ, // FLASH Data bus 8 Bits
43 FL_ADDR, // FLASH Address bus 22 Bits
44 FL_WE_N, // FLASH Write Enable
45 FL_RST_N, // FLASH Reset
46 FL_OE_N, // FLASH Output Enable
47 FL_CE_N, // FLASH Chip Enable
48 / / SRAM Interface /// /
49 SRAM_DQ, // SRAM Data bus 16 Bits
50 SRAM_ADDR, // SRAM Address bus 18 Bits
51 SRAM_UB_N, // SRAM High-byte Data Mask
52 SRAM_LB_N, // SRAM Low-byte Data Mask
53 SRAM_WE_N, // SRAM Write Enable
54 SRAM_CE_N, // SRAM Chip Enable
55 SRAM_OE_N, // SRAM Output Enable
56 / / ISP1362 Interface /// /
57 OTG_DATA, // ISP1362 Data bus 16 Bits
58 OTG_ADDR, // ISP1362 Address 2 Bits
59 OTG_CS_N, // ISP1362 Chip Select
60 OTG_RD_N, // ISP1362 Write
61 OTG_WR_N, // ISP1362 Read
62 OTG_RST_N, // ISP1362 Reset
63 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
64 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
65 OTG_INT0, // ISP1362 Interrupt 0
66 OTG_INT1, // ISP1362 Interrupt 1
67 OTG_DREQ0, // ISP1362 DMA Request 0
68 OTG_DREQ1, // ISP1362 DMA Request 1
69 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
70 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
71 / / LCD Module 16X2 /// /
72 LCD_ON, // LCD Power ON/OFF
73 LCD_BLON, // LCD Back Light ON/OFF
74 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
75 LCD_EN, // LCD Enable
76 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
77 LCD_DATA, // LCD Data bus 8 bits
78 / / SD_Card Interface /// /
79 SD_DAT, // SD Card Data
80 SD_DAT3, // SD Card Data 3
81 SD_CMD, // SD Card Command Signal
82 SD_CLK, // SD Card Clock
83 / / USB JTAG link // //
84 TDI, // CPLD -> FPGA (data in)
85 TCK, // CPLD -> FPGA (clk)
86 TCS, // CPLD -> FPGA (CS)
87 TDO, // FPGA -> CPLD (data out)
88 / / I2C /// /
89 I2C_SDAT, // I2C Data
90 I2C_SCLK, // I2C Clock
91 / / PS2 /// /
92 PS2_DAT, // PS2 Data
93 PS2_CLK, // PS2 Clock
94 / / VGA /// /
95 VGA_CLK, // VGA Clock
96 VGA_HS, // VGA H_SYNC
97 VGA_VS, // VGA V_SYNC
98 VGA_BLANK, // VGA BLANK
99 VGA_SYNC, // VGA SYNC
100 VGA_R, // VGA Red[9:0]
101 VGA_G, // VGA Green[9:0]
102 VGA_B, // VGA Blue[9:0]
103 / / Ethernet Interface
104 ENET_DATA, // DM9000A DATA bus 16Bits
105 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
106 ENET_CS_N, // DM9000A Chip Select
107 ENET_WR_N, // DM9000A Write
108 ENET_RD_N, // DM9000A Read
109 ENET_RST_N, // DM9000A Reset
110 ENET_INT, // DM9000A Interrupt
111 ENET_CLK, // DM9000A Clock 25 MHz
112 / / Audio CODEC
113 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
114 AUD_ADCDAT, // Audio CODEC ADC Data
115 AUD_DACLRCK, // Audio CODEC DAC LR Clock
116 AUD_DACDAT, // Audio CODEC DAC Data
117 AUD_BCLK, // Audio CODEC Bit-Stream Clock
118 AUD_XCK, // Audio CODEC Chip Clock
119 / / TV Decoder
120 TD_DATA, // TV Decoder Data bus 8 bits
121 TD_HS, // TV Decoder H_SYNC
122 TD_VS, // TV Decoder V_SYNC
123 TD_RESET, // TV Decoder Reset
124 / / GPIO /// /
125 GPIO_0, // GPIO Connection 0
126 GPIO_1 // GPIO Connection 1
127 );
128
129 // Clock Input
130 input CLOCK_27; // 27 MHz
131 input CLOCK_50; // 50 MHz
132 input EXT_CLOCK; // External Clock
133 // Push Button
134 input [ 3 : 0 ] KEY; // Pushbutton[3:0]
135 // DPDT Switch
136 input [ 17 : 0 ] SW; // Toggle Switch[17:0]
137 // 7-SEG Dispaly
138 output [ 6 : 0 ] HEX0; // Seven Segment Digit 0
139 output [ 6 : 0 ] HEX1; // Seven Segment Digit 1
140 output [ 6 : 0 ] HEX2; // Seven Segment Digit 2
141 output [ 6 : 0 ] HEX3; // Seven Segment Digit 3
142 output [ 6 : 0 ] HEX4; // Seven Segment Digit 4
143 output [ 6 : 0 ] HEX5; // Seven Segment Digit 5
144 output [ 6 : 0 ] HEX6; // Seven Segment Digit 6
145 output [ 6 : 0 ] HEX7; // Seven Segment Digit 7
146 // LED /// /
147 output [ 8 : 0 ] LEDG; // LED Green[8:0]
148 output [ 17 : 0 ] LEDR; // LED Red[17:0]
149 // UART /// /
150 output UART_TXD; // UART Transmitter
151 input UART_RXD; // UART Receiver
152 // IRDA /// /
153 output IRDA_TXD; // IRDA Transmitter
154 input IRDA_RXD; // IRDA Receiver
155 // SDRAM Interface
156 inout [ 15 : 0 ] DRAM_DQ; // SDRAM Data bus 16 Bits
157 output [ 11 : 0 ] DRAM_ADDR; // SDRAM Address bus 12 Bits
158 output DRAM_LDQM; // SDRAM Low-byte Data Mask
159 output DRAM_UDQM; // SDRAM High-byte Data Mask
160 output DRAM_WE_N; // SDRAM Write Enable
161 output DRAM_CAS_N; // SDRAM Column Address Strobe
162 output DRAM_RAS_N; // SDRAM Row Address Strobe
163 output DRAM_CS_N; // SDRAM Chip Select
164 output DRAM_BA_0; // SDRAM Bank Address 0
165 output DRAM_BA_1; // SDRAM Bank Address 0
166 output DRAM_CLK; // SDRAM Clock
167 output DRAM_CKE; // SDRAM Clock Enable
168 // Flash Interface
169 inout [ 7 : 0 ] FL_DQ; // FLASH Data bus 8 Bits
170 output [ 21 : 0 ] FL_ADDR; // FLASH Address bus 22 Bits
171 output FL_WE_N; // FLASH Write Enable
172 output FL_RST_N; // FLASH Reset
173 output FL_OE_N; // FLASH Output Enable
174 output FL_CE_N; // FLASH Chip Enable
175 // SRAM Interface
176 inout [ 15 : 0 ] SRAM_DQ; // SRAM Data bus 16 Bits
177 output [ 17 : 0 ] SRAM_ADDR; // SRAM Address bus 18 Bits
178 output SRAM_UB_N; // SRAM High-byte Data Mask
179 output SRAM_LB_N; // SRAM Low-byte Data Mask
180 output SRAM_WE_N; // SRAM Write Enable
181 output SRAM_CE_N; // SRAM Chip Enable
182 output SRAM_OE_N; // SRAM Output Enable
183 // ISP1362 Interface
184 inout [ 15 : 0 ] OTG_DATA; // ISP1362 Data bus 16 Bits
185 output [ 1 : 0 ] OTG_ADDR; // ISP1362 Address 2 Bits
186 output OTG_CS_N; // ISP1362 Chip Select
187 output OTG_RD_N; // ISP1362 Write
188 output OTG_WR_N; // ISP1362 Read
189 output OTG_RST_N; // ISP1362 Reset
190 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
191 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
192 input OTG_INT0; // ISP1362 Interrupt 0
193 input OTG_INT1; // ISP1362 Interrupt 1
194 input OTG_DREQ0; // ISP1362 DMA Request 0
195 input OTG_DREQ1; // ISP1362 DMA Request 1
196 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
197 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
198 // LCD Module 16X2 /// /
199 inout [ 7 : 0 ] LCD_DATA; // LCD Data bus 8 bits
200 output LCD_ON; // LCD Power ON/OFF
201 output LCD_BLON; // LCD Back Light ON/OFF
202 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
203 output LCD_EN; // LCD Enable
204 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
205 // SD Card Interface
206 inout SD_DAT; // SD Card Data
207 inout SD_DAT3; // SD Card Data 3
208 inout SD_CMD; // SD Card Command Signal
209 output SD_CLK; // SD Card Clock
210 // I2C // //
211 inout I2C_SDAT; // I2C Data
212 output I2C_SCLK; // I2C Clock
213 // PS2 // //
214 input PS2_DAT; // PS2 Data
215 input PS2_CLK; // PS2 Clock
216 // USB JTAG link /// /
217 input TDI; // CPLD -> FPGA (data in)
218 input TCK; // CPLD -> FPGA (clk)
219 input TCS; // CPLD -> FPGA (CS)
220 output TDO; // FPGA -> CPLD (data out)
221 // VGA /// /
222 output VGA_CLK; // VGA Clock
223 output VGA_HS; // VGA H_SYNC
224 output VGA_VS; // VGA V_SYNC
225 output VGA_BLANK; // VGA BLANK
226 output VGA_SYNC; // VGA SYNC
227 output [ 9 : 0 ] VGA_R; // VGA Red[9:0]
228 output [ 9 : 0 ] VGA_G; // VGA Green[9:0]
229 output [ 9 : 0 ] VGA_B; // VGA Blue[9:0]
230 // Ethernet Interface /// /
231 inout [ 15 : 0 ] ENET_DATA; // DM9000A DATA bus 16Bits
232 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
233 output ENET_CS_N; // DM9000A Chip Select
234 output ENET_WR_N; // DM9000A Write
235 output ENET_RD_N; // DM9000A Read
236 output ENET_RST_N; // DM9000A Reset
237 input ENET_INT; // DM9000A Interrupt
238 output ENET_CLK; // DM9000A Clock 25 MHz
239 // Audio CODEC /// /
240 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
241 input AUD_ADCDAT; // Audio CODEC ADC Data
242 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
243 output AUD_DACDAT; // Audio CODEC DAC Data
244 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
245 output AUD_XCK; // Audio CODEC Chip Clock
246 // TV Devoder /// /
247 input [ 7 : 0 ] TD_DATA; // TV Decoder Data bus 8 bits
248 input TD_HS; // TV Decoder H_SYNC
249 input TD_VS; // TV Decoder V_SYNC
250 output TD_RESET; // TV Decoder Reset
251 // GPIO // //
252 inout [ 35 : 0 ] GPIO_0; // GPIO Connection 0
253 inout [ 35 : 0 ] GPIO_1; // GPIO Connection 1
254
255 // Turn on all display
256 assign LCD_ON = 1 ' b1;
257 assign LCD_BLON = 1 ' b1;
258
259 // All inout port turn to tri-state
260 assign DRAM_DQ = 16 ' hzzzz;
261 assign FL_DQ = 8 ' hzz;
262 assign SRAM_DQ = 16 ' hzzzz;
263 assign OTG_DATA = 16 ' hzzzz;
264 assign LCD_DATA = 8 ' hzz;
265 assign SD_DAT = 1 ' bz;
266 assign ENET_DATA = 16 ' hzzzz;
267 assign AUD_ADCLRCK = 1 ' bz;
268 assign AUD_DACLRCK = 1 ' bz;
269 assign AUD_BCLK = 1 ' bz;
270 assign TD_RESET = 1 ' b1;
271
272 For TFT LCD Module / //
273 wire [ 7 : 0 ] LCM_DATA; // LCM Data 8 Bits
274 wire LCM_GRST; // LCM Global Reset
275 wire LCM_SHDB; // LCM Sleep Mode
276 wire LCM_DCLK; // LCM Clcok
277 wire LCM_HSYNC; // LCM HSYNC
278 wire LCM_VSYNC; // LCM VSYNC
279 wire LCM_SCLK; // LCM I2C Clock
280 wire LCM_SDAT; // LCM I2C Data
281 wire LCM_SCEN; // LCM I2C Enable
282 wire CLK_18;
283
284 assign GPIO_0[ 18 ] = LCM_DATA[ 6 ];
285 assign GPIO_0[ 19 ] = LCM_DATA[ 7 ];
286 assign GPIO_0[ 20 ] = LCM_DATA[ 4 ];
287 assign GPIO_0[ 21 ] = LCM_DATA[ 5 ];
288 assign GPIO_0[ 22 ] = LCM_DATA[ 2 ];
289 assign GPIO_0[ 23 ] = LCM_DATA[ 3 ];
290 assign GPIO_0[ 24 ] = LCM_DATA[ 0 ];
291 assign GPIO_0[ 25 ] = LCM_DATA[ 1 ];
292 assign GPIO_0[ 26 ] = LCM_VSYNC;
293 assign GPIO_0[ 28 ] = LCM_SCLK;
294 assign GPIO_0[ 29 ] = LCM_DCLK;
295 assign GPIO_0[ 30 ] = LCM_GRST;
296 assign GPIO_0[ 31 ] = LCM_SHDB;
297 assign GPIO_0[ 33 ] = LCM_SCEN;
298 assign GPIO_0[ 34 ] = LCM_SDAT;
299 assign GPIO_0[ 35 ] = LCM_HSYNC;
300
301 For CMOS Sensor 1 / //
302 wire [ 9 : 0 ] CCD_DATA;
303 wire CCD_SDAT;
304 wire CCD_SCLK;
305 wire CCD_FLASH;
306 wire CCD_FVAL;
307 wire CCD_LVAL;
308 wire CCD_PIXCLK;
309 reg CCD_MCLK; // CCD Master Clock
310
311 wire [ 15 : 0 ] Read_DATA1;
312 wire [ 15 : 0 ] Read_DATA2;
313 wire [ 9 : 0 ] mCCD_DATA;
314 wire mCCD_DVAL;
315 wire mCCD_DVAL_d;
316 wire [ 10 : 0 ] X_Cont;
317 wire [ 10 : 0 ] Y_Cont;
318 wire [ 9 : 0 ] X_ADDR;
319 wire [ 31 : 0 ] Frame_Cont;
320 wire [ 9 : 0 ] mCCD_R;
321 wire [ 9 : 0 ] mCCD_G;
322 wire [ 9 : 0 ] mCCD_B;
323 wire DLY_RST_0;
324 wire DLY_RST_1;
325 wire DLY_RST_2;
326 wire Read;
327 reg [ 9 : 0 ] rCCD_DATA;
328 reg rCCD_LVAL;
329 reg rCCD_FVAL;
330 wire [ 9 : 0 ] sCCD_R;
331 wire [ 9 : 0 ] sCCD_G;
332 wire [ 9 : 0 ] sCCD_B;
333 wire sCCD_DVAL;
334
335 assign CCD_DATA[ 0 ] = GPIO_1[ 0 ];
336 assign CCD_DATA[ 1 ] = GPIO_1[ 1 ];
337 assign CCD_DATA[ 2 ] = GPIO_1[ 5 ];
338 assign CCD_DATA[ 3 ] = GPIO_1[ 3 ];
339 assign CCD_DATA[ 4 ] = GPIO_1[ 2 ];
340 assign CCD_DATA[ 5 ] = GPIO_1[ 4 ];
341 assign CCD_DATA[ 6 ] = GPIO_1[ 6 ];
342 assign CCD_DATA[ 7 ] = GPIO_1[ 7 ];
343 assign CCD_DATA[ 8 ] = GPIO_1[ 8 ];
344 assign CCD_DATA[ 9 ] = GPIO_1[ 9 ];
345 assign GPIO_1[ 11 ] = CCD_MCLK;
346 assign GPIO_1[ 15 ] = CCD_SDAT;
347 assign GPIO_1[ 14 ] = CCD_SCLK;
348 assign CCD_FVAL = GPIO_1[ 13 ];
349 assign CCD_LVAL = GPIO_1[ 12 ];
350 assign CCD_PIXCLK = GPIO_1[ 10 ];
351
352 assign LEDR = SW;
353 assign LEDG = Y_Cont;
354
355 always@(posedge CLOCK_50)
356 CCD_MCLK <= ~ CCD_MCLK;
357
358 always@(posedge CCD_PIXCLK)
359 begin
360 rCCD_DATA <= CCD_DATA;
361 rCCD_LVAL <= CCD_LVAL;
362 rCCD_FVAL <= CCD_FVAL;
363 end
364
365 LCM_PLL u0 (
366 .inclk0(CLOCK_27),
367 .c0(CLK_18)
368 );
369
370 LCM_Controller u1 (
371 // Host Side
372 .iRed(Read_DATA2[ 9 : 2 ]),
373 .iGreen({Read_DATA1[ 14 : 10 ], Read_DATA2[ 14 : 12 ]}),
374 .iBlue(Read_DATA1[ 9 : 2 ]),
375 // LCM Side
376 .LCM_DATA(LCM_DATA),
377 .LCM_VSYNC(LCM_VSYNC),
378 .LCM_HSYNC(LCM_HSYNC),
379 .LCM_DCLK(LCM_DCLK),
380 .LCM_SHDB(LCM_SHDB),
381 .LCM_GRST(LCM_GRST),
382 // Control Signals
383 .oDATA_REQ(Read),
384 .iCLK(CLK_18),
385 .iRST_N(DLY_RST_2)
386 );
387
388 Reset_Delay u2 (
389 .iCLK(CLOCK_50),
390 .iRST(KEY[ 0 ]),
391 .oRST_0(DLY_RST_0),
392 .oRST_1(DLY_RST_1),
393 .oRST_2(DLY_RST_2)
394 );
395
396 CCD_Capture u3 (
397 .oDATA(mCCD_DATA),
398 .oDVAL(mCCD_DVAL),
399 .oX_Cont(X_Cont),
400 .oY_Cont(Y_Cont),
401 .oFrame_Cont(Frame_Cont),
402 .iDATA(rCCD_DATA),
403 .iFVAL(rCCD_FVAL),
404 .iLVAL(rCCD_LVAL),
405 .iSTART( ! KEY[ 3 ]),
406 .iEND( ! KEY[ 2 ]),
407 .iCLK(CCD_PIXCLK),
408 .iRST(DLY_RST_1)
409 );
410
411 RAW2RGB u4 (
412 .oRed(mCCD_R),
413 .oGreen(mCCD_G),
414 .oBlue(mCCD_B),
415 .oDVAL(mCCD_DVAL_d),
416 .iX_Cont(X_Cont),
417 .iY_Cont(Y_Cont),
418 .iDATA(mCCD_DATA),
419 .iDVAL(mCCD_DVAL),
420 .iCLK(CCD_PIXCLK),
421 .iRST(DLY_RST_1)
422 );
423
424 SEG7_LUT_8 u5 (
425 .oSEG0(HEX0),
426 .oSEG1(HEX1),
427 .oSEG2(HEX2),
428 .oSEG3(HEX3),
429 .oSEG4(HEX4),
430 .oSEG5(HEX5),
431 .oSEG6(HEX6),
432 .oSEG7(HEX7),
433 .iDIG(Frame_Cont)
434 );
435
436 Sdram_Control_4Port u6 (
437 // HOST Side
438 .REF_CLK(CLOCK_50),
439 .RESET_N( 1 ' b1),
440 // FIFO Write Side 1
441 .WR1_DATA({sCCD_G[ 9 : 5 ], sCCD_B[ 9 : 0 ]}),
442 .WR1(sCCD_DVAL),
443 .WR1_ADDR( 0 ),
444 .WR1_MAX_ADDR( 320 * 256 ),
445 .WR1_LENGTH( 9 ' h100),
446 .WR1_LOAD( ! DLY_RST_0),
447 .WR1_CLK(CCD_PIXCLK),
448 // FIFO Write Side 2
449 .WR2_DATA({sCCD_G[ 4 : 0 ], sCCD_R[ 9 : 0 ]}),
450 .WR2(sCCD_DVAL),
451 .WR2_ADDR( 22 ' h100000),
452 .WR2_MAX_ADDR( 22 ' h100000+320*256),
453 .WR2_LENGTH( 9 ' h100),
454 .WR2_LOAD( ! DLY_RST_0),
455 .WR2_CLK(CCD_PIXCLK),
456 // FIFO Read Side 1
457 .RD1_DATA(Read_DATA1),
458 .RD1(Read),
459 .RD1_ADDR( 320 * 8 ),
460 .RD1_MAX_ADDR( 320 * 248 ),
461 .RD1_LENGTH( 9 ' h100),
462 .RD1_LOAD( ! DLY_RST_0),
463 .RD1_CLK(CLK_18),
464 // FIFO Read Side 2
465 .RD2_DATA(Read_DATA2),
466 .RD2(Read),
467 .RD2_ADDR( 22 ' h100000+320*8),
468 .RD2_MAX_ADDR( 22 ' h100000+320*248),
469 .RD2_LENGTH( 9 ' h100),
470 .RD2_LOAD( ! DLY_RST_0),
471 .RD2_CLK(CLK_18),
472 // SDRAM Side
473 .SA(DRAM_ADDR),
474 .BA({DRAM_BA_1,DRAM_BA_0}),
475 .CS_N(DRAM_CS_N),
476 .CKE(DRAM_CKE),
477 .RAS_N(DRAM_RAS_N),
478 .CAS_N(DRAM_CAS_N),
479 .WE_N(DRAM_WE_N),
480 .DQ(DRAM_DQ),
481 .DQM({DRAM_UDQM,DRAM_LDQM}),
482 .SDR_CLK(DRAM_CLK)
483 );
484
485 I2C_CCD_Config u7 (
486 // Host Side
487 .iCLK(CLOCK_50),
488 .iRST_N(KEY[ 1 ]),
489 .iExposure(SW[ 15 : 0 ]),
490 // I2C Side
491 .I2C_SCLK(CCD_SCLK),
492 .I2C_SDAT(CCD_SDAT)
493 );
494
495 I2S_LCM_Config u8 (
496 // Host Side
497 .iCLK(CLOCK_50),
498 .iRST_N(KEY[ 0 ]),
499 // I2C Side
500 .I2S_SCLK(LCM_SCLK),
501 .I2S_SDAT(LCM_SDAT),
502 .I2S_SCEN(LCM_SCEN)
503 );
504
505 I2C_AV_Config u9 (
506 // Host Side
507 .iCLK(CLOCK_50),
508 .iRST_N(KEY[ 0 ]),
509 // I2C Side
510 .I2C_SCLK(I2C_SCLK),
511 .I2C_SDAT(I2C_SDAT)
512 );
513
514 Mirror_Col u10 (
515 // Input Side
516 .iCCD_R(mCCD_R),
517 .iCCD_G(mCCD_G),
518 .iCCD_B(mCCD_B),
519 .iCCD_DVAL(mCCD_DVAL_d),
520 .iCCD_PIXCLK(CCD_PIXCLK),
521 .iRST_N(DLY_RST_1),
522 // Output Side
523 .oCCD_R(sCCD_R),
524 .oCCD_G(sCCD_G),
525 .oCCD_B(sCCD_B),
526 .oCCD_DVAL(sCCD_DVAL)
527 );
528
529 endmodule
CCD_Capture.v
1
module CCD_Capture (
2 oDATA,
3 oDVAL,
4 oX_Cont,
5 oY_Cont,
6 oFrame_Cont,
7 iDATA,
8 iFVAL,
9 iLVAL,
10 iSTART,
11 iEND,
12 iCLK,
13 iRST
14 );
15
16 input [ 9 : 0 ] iDATA;
17 input iFVAL;
18 input iLVAL;
19 input iSTART;
20 input iEND;
21 input iCLK;
22 input iRST;
23 output [ 9 : 0 ] oDATA;
24 output [ 10 : 0 ] oX_Cont;
25 output [ 10 : 0 ] oY_Cont;
26 output [ 31 : 0 ] oFrame_Cont;
27 output oDVAL;
28 reg Pre_FVAL;
29 reg mCCD_FVAL;
30 reg mCCD_LVAL;
31 reg [ 9 : 0 ] mCCD_DATA;
32 reg [ 10 : 0 ] X_Cont;
33 reg [ 10 : 0 ] Y_Cont;
34 reg [ 31 : 0 ] Frame_Cont;
35 reg mSTART;
36
37 assign oX_Cont = X_Cont;
38 assign oY_Cont = Y_Cont;
39 assign oFrame_Cont = Frame_Cont;
40 assign oDATA = mCCD_DATA;
41 assign oDVAL = mCCD_FVAL & mCCD_LVAL;
42
43 always@(posedge iCLK or negedge iRST)
44 begin
45 if ( ! iRST)
46 mSTART <= 0 ;
47 else
48 begin
49 if (iSTART)
50 mSTART <= 1 ;
51
52 if (iEND)
53 mSTART <= 0 ;
54 end
55 end
56
57 always@(posedge iCLK or negedge iRST)
58 begin
59 if ( ! iRST)
60 begin
61 Pre_FVAL <= 0 ;
62 mCCD_FVAL <= 0 ;
63 mCCD_LVAL <= 0 ;
64 mCCD_DATA <= 0 ;
65 X_Cont <= 0 ;
66 Y_Cont <= 0 ;
67 end
68 else
69 begin
70 Pre_FVAL <= iFVAL;
71 if (({Pre_FVAL,iFVAL} == 2 ' b01) && mSTART)
72 mCCD_FVAL <= 1 ;
73 else if ({Pre_FVAL,iFVAL} == 2 ' b10)
74 mCCD_FVAL <= 0 ;
75
76 mCCD_LVAL <= iLVAL;
77 mCCD_DATA <= iDATA;
78
79 if (mCCD_FVAL)
80 begin
81 if (mCCD_LVAL)
82 begin
83 if (X_Cont < 1279 )
84 X_Cont <= X_Cont + 1 ;
85 else
86 begin
87 X_Cont <= 0 ;
88 Y_Cont <= Y_Cont + 1 ;
89 end
90 end
91 end
92 else
93 begin
94 X_Cont <= 0 ;
95 Y_Cont <= 0 ;
96 end
97 end
98 end
99
100 always@(posedge iCLK or negedge iRST)
101 begin
102 if ( ! iRST)
103 Frame_Cont <= 0 ;
104 else
105 begin
106 if (({Pre_FVAL,iFVAL} == 2 ' b01) && mSTART)
107 Frame_Cont <= Frame_Cont + 1 ;
108 end
109 end
110
111 endmodule
2 oDATA,
3 oDVAL,
4 oX_Cont,
5 oY_Cont,
6 oFrame_Cont,
7 iDATA,
8 iFVAL,
9 iLVAL,
10 iSTART,
11 iEND,
12 iCLK,
13 iRST
14 );
15
16 input [ 9 : 0 ] iDATA;
17 input iFVAL;
18 input iLVAL;
19 input iSTART;
20 input iEND;
21 input iCLK;
22 input iRST;
23 output [ 9 : 0 ] oDATA;
24 output [ 10 : 0 ] oX_Cont;
25 output [ 10 : 0 ] oY_Cont;
26 output [ 31 : 0 ] oFrame_Cont;
27 output oDVAL;
28 reg Pre_FVAL;
29 reg mCCD_FVAL;
30 reg mCCD_LVAL;
31 reg [ 9 : 0 ] mCCD_DATA;
32 reg [ 10 : 0 ] X_Cont;
33 reg [ 10 : 0 ] Y_Cont;
34 reg [ 31 : 0 ] Frame_Cont;
35 reg mSTART;
36
37 assign oX_Cont = X_Cont;
38 assign oY_Cont = Y_Cont;
39 assign oFrame_Cont = Frame_Cont;
40 assign oDATA = mCCD_DATA;
41 assign oDVAL = mCCD_FVAL & mCCD_LVAL;
42
43 always@(posedge iCLK or negedge iRST)
44 begin
45 if ( ! iRST)
46 mSTART <= 0 ;
47 else
48 begin
49 if (iSTART)
50 mSTART <= 1 ;
51
52 if (iEND)
53 mSTART <= 0 ;
54 end
55 end
56
57 always@(posedge iCLK or negedge iRST)
58 begin
59 if ( ! iRST)
60 begin
61 Pre_FVAL <= 0 ;
62 mCCD_FVAL <= 0 ;
63 mCCD_LVAL <= 0 ;
64 mCCD_DATA <= 0 ;
65 X_Cont <= 0 ;
66 Y_Cont <= 0 ;
67 end
68 else
69 begin
70 Pre_FVAL <= iFVAL;
71 if (({Pre_FVAL,iFVAL} == 2 ' b01) && mSTART)
72 mCCD_FVAL <= 1 ;
73 else if ({Pre_FVAL,iFVAL} == 2 ' b10)
74 mCCD_FVAL <= 0 ;
75
76 mCCD_LVAL <= iLVAL;
77 mCCD_DATA <= iDATA;
78
79 if (mCCD_FVAL)
80 begin
81 if (mCCD_LVAL)
82 begin
83 if (X_Cont < 1279 )
84 X_Cont <= X_Cont + 1 ;
85 else
86 begin
87 X_Cont <= 0 ;
88 Y_Cont <= Y_Cont + 1 ;
89 end
90 end
91 end
92 else
93 begin
94 X_Cont <= 0 ;
95 Y_Cont <= 0 ;
96 end
97 end
98 end
99
100 always@(posedge iCLK or negedge iRST)
101 begin
102 if ( ! iRST)
103 Frame_Cont <= 0 ;
104 else
105 begin
106 if (({Pre_FVAL,iFVAL} == 2 ' b01) && mSTART)
107 Frame_Cont <= Frame_Cont + 1 ;
108 end
109 end
110
111 endmodule
RAW2RGB.v
1
module RAW2RGB (
2 oRed,
3 oGreen,
4 oBlue,
5 oDVAL,
6 iX_Cont,
7 iY_Cont,
8 iDATA,
9 iDVAL,
10 iCLK,
11 iRST
12 );
13
14 input [ 10 : 0 ] iX_Cont;
15 input [ 10 : 0 ] iY_Cont;
16 input [ 9 : 0 ] iDATA;
17 input iDVAL;
18 input iCLK;
19 input iRST;
20 output [ 9 : 0 ] oRed;
21 output [ 9 : 0 ] oGreen;
22 output [ 9 : 0 ] oBlue;
23 output oDVAL;
24 wire [ 9 : 0 ] mDATA_0;
25 wire [ 9 : 0 ] mDATA_1;
26 reg [ 9 : 0 ] mDATAd_0;
27 reg [ 9 : 0 ] mDATAd_1;
28 reg [ 9 : 0 ] mCCD_R;
29 reg [ 10 : 0 ] mCCD_G;
30 reg [ 9 : 0 ] mCCD_B;
31 reg mDVAL;
32
33 assign oRed = mCCD_R[ 9 : 0 ];
34 assign oGreen = mCCD_G[ 10 : 1 ];
35 assign oBlue = mCCD_B[ 9 : 0 ];
36 assign oDVAL = mDVAL;
37
38 Line_Buffer u0 (
39 .clken(iDVAL),
40 .clock(iCLK),
41 .shiftin(iDATA),
42 .taps0x(mDATA_1),
43 .taps1x(mDATA_0)
44 );
45
46 always@(posedge iCLK or negedge iRST)
47 begin
48 if ( ! iRST)
49 begin
50 mCCD_R <= 0 ;
51 mCCD_G <= 0 ;
52 mCCD_B <= 0 ;
53 mDATAd_0 <= 0 ;
54 mDATAd_1 <= 0 ;
55 mDVAL <= 0 ;
56 end
57 else
58 begin
59 mDATAd_0 <= mDATA_0;
60 mDATAd_1 <= mDATA_1;
61 mDVAL <= {iY_Cont[ 1 ] | iY_Cont[ 0 ] | iX_Cont[ 1 ] | iX_Cont[ 0 ]} ? 1 ' b0 : iDVAL;
62 if ({iY_Cont[ 0 ],iX_Cont[ 0 ]} == 2 ' b01)
63 begin
64 mCCD_R <= mDATA_0;
65 mCCD_G <= mDATAd_0 + mDATA_1;
66 mCCD_B <= mDATAd_1;
67 end
68 else if ({iY_Cont[ 0 ],iX_Cont[ 0 ]} == 2 ' b00)
69 begin
70 mCCD_R <= mDATAd_0;
71 mCCD_G <= mDATA_0 + mDATAd_1;
72 mCCD_B <= mDATA_1;
73 end
74 else if ({iY_Cont[ 0 ], iX_Cont[ 0 ]} == 2 ' b11)
75 begin
76 mCCD_R <= mDATA_1;
77 mCCD_G <= mDATA_0 + mDATAd_1;
78 mCCD_B <= mDATAd_0;
79 end
80 else if ({iY_Cont[ 0 ], iX_Cont[ 0 ]} == 2 ' b10)
81 begin
82 mCCD_R <= mDATAd_1;
83 mCCD_G <= mDATAd_0 + mDATA_1;
84 mCCD_B <= mDATA_0;
85 end
86 end
87 end
88
89 endmodule
2 oRed,
3 oGreen,
4 oBlue,
5 oDVAL,
6 iX_Cont,
7 iY_Cont,
8 iDATA,
9 iDVAL,
10 iCLK,
11 iRST
12 );
13
14 input [ 10 : 0 ] iX_Cont;
15 input [ 10 : 0 ] iY_Cont;
16 input [ 9 : 0 ] iDATA;
17 input iDVAL;
18 input iCLK;
19 input iRST;
20 output [ 9 : 0 ] oRed;
21 output [ 9 : 0 ] oGreen;
22 output [ 9 : 0 ] oBlue;
23 output oDVAL;
24 wire [ 9 : 0 ] mDATA_0;
25 wire [ 9 : 0 ] mDATA_1;
26 reg [ 9 : 0 ] mDATAd_0;
27 reg [ 9 : 0 ] mDATAd_1;
28 reg [ 9 : 0 ] mCCD_R;
29 reg [ 10 : 0 ] mCCD_G;
30 reg [ 9 : 0 ] mCCD_B;
31 reg mDVAL;
32
33 assign oRed = mCCD_R[ 9 : 0 ];
34 assign oGreen = mCCD_G[ 10 : 1 ];
35 assign oBlue = mCCD_B[ 9 : 0 ];
36 assign oDVAL = mDVAL;
37
38 Line_Buffer u0 (
39 .clken(iDVAL),
40 .clock(iCLK),
41 .shiftin(iDATA),
42 .taps0x(mDATA_1),
43 .taps1x(mDATA_0)
44 );
45
46 always@(posedge iCLK or negedge iRST)
47 begin
48 if ( ! iRST)
49 begin
50 mCCD_R <= 0 ;
51 mCCD_G <= 0 ;
52 mCCD_B <= 0 ;
53 mDATAd_0 <= 0 ;
54 mDATAd_1 <= 0 ;
55 mDVAL <= 0 ;
56 end
57 else
58 begin
59 mDATAd_0 <= mDATA_0;
60 mDATAd_1 <= mDATA_1;
61 mDVAL <= {iY_Cont[ 1 ] | iY_Cont[ 0 ] | iX_Cont[ 1 ] | iX_Cont[ 0 ]} ? 1 ' b0 : iDVAL;
62 if ({iY_Cont[ 0 ],iX_Cont[ 0 ]} == 2 ' b01)
63 begin
64 mCCD_R <= mDATA_0;
65 mCCD_G <= mDATAd_0 + mDATA_1;
66 mCCD_B <= mDATAd_1;
67 end
68 else if ({iY_Cont[ 0 ],iX_Cont[ 0 ]} == 2 ' b00)
69 begin
70 mCCD_R <= mDATAd_0;
71 mCCD_G <= mDATA_0 + mDATAd_1;
72 mCCD_B <= mDATA_1;
73 end
74 else if ({iY_Cont[ 0 ], iX_Cont[ 0 ]} == 2 ' b11)
75 begin
76 mCCD_R <= mDATA_1;
77 mCCD_G <= mDATA_0 + mDATAd_1;
78 mCCD_B <= mDATAd_0;
79 end
80 else if ({iY_Cont[ 0 ], iX_Cont[ 0 ]} == 2 ' b10)
81 begin
82 mCCD_R <= mDATAd_1;
83 mCCD_G <= mDATAd_0 + mDATA_1;
84 mCCD_B <= mDATA_0;
85 end
86 end
87 end
88
89 endmodule
Sdram_Control_4Port.v
1
module Sdram_Control_4Port (
2 // HOST Side
3 REF_CLK,
4 RESET_N,
5 // FIFO Write Side 1
6 WR1_DATA,
7 WR1,
8 WR1_ADDR,
9 WR1_MAX_ADDR,
10 WR1_LENGTH,
11 WR1_LOAD,
12 WR1_CLK,
13 WR1_FULL,
14 WR1_USE,
15 // FIFO Write Side 2
16 WR2_DATA,
17 WR2,
18 WR2_ADDR,
19 WR2_MAX_ADDR,
20 WR2_LENGTH,
21 WR2_LOAD,
22 WR2_CLK,
23 WR2_FULL,
24 WR2_USE,
25 // FIFO Read Side 1
26 RD1_DATA,
27 RD1,
28 RD1_ADDR,
29 RD1_MAX_ADDR,
30 RD1_LENGTH,
31 RD1_LOAD,
32 RD1_CLK,
33 RD1_EMPTY,
34 RD1_USE,
35 // FIFO Read Side 2
36 RD2_DATA,
37 RD2,
38 RD2_ADDR,
39 RD2_MAX_ADDR,
40 RD2_LENGTH,
41 RD2_LOAD,
42 RD2_CLK,
43 RD2_EMPTY,
44 RD2_USE,
45 // SDRAM Side
46 SA,
47 BA,
48 CS_N,
49 CKE,
50 RAS_N,
51 CAS_N,
52 WE_N,
53 DQ,
54 DQM,
55 SDR_CLK
56 );
57
58 `include " Sdram_Params.h "
59 // HOST Side
60 input REF_CLK; // System Clock
61 input RESET_N; // System Reset
62
63 // FIFO Write Side 1
64 input [`DSIZE - 1 : 0 ] WR1_DATA; // Data input
65 input WR1; // Write Request
66 input [`ASIZE - 1 : 0 ] WR1_ADDR; // Write start address
67 input [`ASIZE - 1 : 0 ] WR1_MAX_ADDR; // Write max address
68 input [ 8 : 0 ] WR1_LENGTH; // Write length
69 input WR1_LOAD; // Write register load & fifo clear
70 input WR1_CLK; // Write fifo clock
71 output WR1_FULL; // Write fifo full
72 output [ 8 : 0 ] WR1_USE; // Write fifo usedw
73
74 // FIFO Write Side 2
75 input [`DSIZE - 1 : 0 ] WR2_DATA; // Data input
76 input WR2; // Write Request
77 input [`ASIZE - 1 : 0 ] WR2_ADDR; // Write start address
78 input [`ASIZE - 1 : 0 ] WR2_MAX_ADDR; // Write max address
79 input [ 8 : 0 ] WR2_LENGTH; // Write length
80 input WR2_LOAD; // Write register load & fifo clear
81 input WR2_CLK; // Write fifo clock
82 output WR2_FULL; // Write fifo full
83 output [ 8 : 0 ] WR2_USE; // Write fifo usedw
84
85 // FIFO Read Side 1
86 output [`DSIZE - 1 : 0 ] RD1_DATA; // Data output
87 input RD1; // Read Request
88 input [`ASIZE - 1 : 0 ] RD1_ADDR; // Read start address
89 input [`ASIZE - 1 : 0 ] RD1_MAX_ADDR; // Read max address
90 input [ 8 : 0 ] RD1_LENGTH; // Read length
91 input RD1_LOAD; // Read register load & fifo clear
92 input RD1_CLK; // Read fifo clock
93 output RD1_EMPTY; // Read fifo empty
94 output [ 8 : 0 ] RD1_USE; // Read fifo usedw
95
96 // FIFO Read Side 2
97 output [`DSIZE - 1 : 0 ] RD2_DATA; // Data output
98 input RD2; // Read Request
99 input [`ASIZE - 1 : 0 ] RD2_ADDR; // Read start address
100 input [`ASIZE - 1 : 0 ] RD2_MAX_ADDR; // Read max address
101 input [ 8 : 0 ] RD2_LENGTH; // Read length
102 input RD2_LOAD; // Read register load & fifo clear
103 input RD2_CLK; // Read fifo clock
104 output RD2_EMPTY; // Read fifo empty
105 output [ 8 : 0 ] RD2_USE; // Read fifo usedw
106
107 // SDRAM Side
108 output [ 11 : 0 ] SA; // SDRAM address output
109 output [ 1 : 0 ] BA; // SDRAM bank address
110 output [ 1 : 0 ] CS_N; // SDRAM Chip Selects
111 output CKE; // SDRAM clock enable
112 output RAS_N; // SDRAM Row address Strobe
113 output CAS_N; // SDRAM Column address Strobe
114 output WE_N; // SDRAM write enable
115 inout [`DSIZE - 1 : 0 ] DQ; // SDRAM data bus
116 output [`DSIZE / 8 - 1 : 0 ] DQM; // SDRAM data mask lines
117 output SDR_CLK; // SDRAM clock
118
119 // Internal Registers/Wires
120 // Controller
121 reg [`ASIZE - 1 : 0 ] mADDR; // Internal address
122 reg [ 8 : 0 ] mLENGTH; // Internal length
123 reg [`ASIZE - 1 : 0 ] rWR1_ADDR; // Register write address
124 reg [`ASIZE - 1 : 0 ] rWR1_MAX_ADDR; // Register max write address
125 reg [ 8 : 0 ] rWR1_LENGTH; // Register write length
126 reg [`ASIZE - 1 : 0 ] rWR2_ADDR; // Register write address
127 reg [`ASIZE - 1 : 0 ] rWR2_MAX_ADDR; // Register max write address
128 reg [ 8 : 0 ] rWR2_LENGTH; // Register write length
129 reg [`ASIZE - 1 : 0 ] rRD1_ADDR; // Register read address
130 reg [`ASIZE - 1 : 0 ] rRD1_MAX_ADDR; // Register max read address
131 reg [ 8 : 0 ] rRD1_LENGTH; // Register read length
132 reg [`ASIZE - 1 : 0 ] rRD2_ADDR; // Register read address
133 reg [`ASIZE - 1 : 0 ] rRD2_MAX_ADDR; // Register max read address
134 reg [ 8 : 0 ] rRD2_LENGTH; // Register read length
135 reg [ 1 : 0 ] WR_MASK; // Write port active mask
136 reg [ 1 : 0 ] RD_MASK; // Read port active mask
137 reg mWR_DONE; // Flag write done, 1 pulse SDR_CLK
138 reg mRD_DONE; // Flag read done, 1 pulse SDR_CLK
139 reg mWR,Pre_WR; // Internal WR edge capture
140 reg mRD,Pre_RD; // Internal RD edge capture
141 reg [ 9 : 0 ] ST; // Controller status
142 reg [ 1 : 0 ] CMD; // Controller command
143 reg PM_STOP; // Flag page mode stop
144 reg PM_DONE; // Flag page mode done
145 reg Read; // Flag read active
146 reg Write; // Flag write active
147 reg [`DSIZE - 1 : 0 ] mDATAOUT; // Controller Data output
148 wire [`DSIZE - 1 : 0 ] mDATAIN; // Controller Data input
149 wire [`DSIZE - 1 : 0 ] mDATAIN1; // Controller Data input 1
150 wire [`DSIZE - 1 : 0 ] mDATAIN2; // Controller Data input 2
151 wire CMDACK; // Controller command acknowledgement
152
153 // DRAM Control
154 reg [`DSIZE / 8 - 1 : 0 ] DQM; // SDRAM data mask lines
155 reg [ 11 : 0 ] SA; // SDRAM address output
156 reg [ 1 : 0 ] BA; // SDRAM bank address
157 reg [ 1 : 0 ] CS_N; // SDRAM Chip Selects
158 reg CKE; // SDRAM clock enable
159 reg RAS_N; // SDRAM Row address Strobe
160 reg CAS_N; // SDRAM Column address Strobe
161 reg WE_N; // SDRAM write enable
162 wire [`DSIZE - 1 : 0 ] DQOUT; // SDRAM data out link
163 wire [`DSIZE / 8 - 1 : 0 ] IDQM; // SDRAM data mask lines
164 wire [ 11 : 0 ] ISA; // SDRAM address output
165 wire [ 1 : 0 ] IBA; // SDRAM bank address
166 wire [ 1 : 0 ] ICS_N; // SDRAM Chip Selects
167 wire ICKE; // SDRAM clock enable
168 wire IRAS_N; // SDRAM Row address Strobe
169 wire ICAS_N; // SDRAM Column address Strobe
170 wire IWE_N; // SDRAM write enable
171
172 // FIFO Control
173 reg OUT_VALID; // Output data request to read side fifo
174 reg IN_REQ; // Input data request to write side fifo
175 wire [ 8 : 0 ] write_side_fifo_rusedw1;
176 wire [ 8 : 0 ] read_side_fifo_wusedw1;
177 wire [ 8 : 0 ] write_side_fifo_rusedw2;
178 wire [ 8 : 0 ] read_side_fifo_wusedw2;
179
180 // DRAM Internal Control
181 wire [`ASIZE - 1 : 0 ] saddr;
182 wire load_mode;
183 wire nop;
184 wire reada;
185 wire writea;
186 wire refresh;
187 wire precharge;
188 wire oe;
189 wire ref_ack;
190 wire ref_req;
191 wire init_req;
192 wire cm_ack;
193 wire active;
194 wire CLK;
195
196
197 Sdram_PLL sdram_pll1 (
198 .inclk0(REF_CLK),
199 .c0(CLK),
200 .c1(SDR_CLK)
201 );
202
203 control_interface control1 (
204 .CLK(CLK),
205 .RESET_N(RESET_N),
206 .CMD(CMD),
207 .ADDR(mADDR),
208 .REF_ACK(ref_ack),
209 .CM_ACK(cm_ack),
210 .NOP(nop),
211 .READA(reada),
212 .WRITEA(writea),
213 .REFRESH(refresh),
214 .PRECHARGE(precharge),
215 .LOAD_MODE(load_mode),
216 .SADDR(saddr),
217 .REF_REQ(ref_req),
218 .INIT_REQ(init_req),
219 .CMD_ACK(CMDACK)
220 );
221
222 command command1(
223 .CLK(CLK),
224 .RESET_N(RESET_N),
225 .SADDR(saddr),
226 .NOP(nop),
227 .READA(reada),
228 .WRITEA(writea),
229 .REFRESH(refresh),
230 .LOAD_MODE(load_mode),
231 .PRECHARGE(precharge),
232 .REF_REQ(ref_req),
233 .INIT_REQ(init_req),
234 .REF_ACK(ref_ack),
235 .CM_ACK(cm_ack),
236 .OE(oe),
237 .PM_STOP(PM_STOP),
238 .PM_DONE(PM_DONE),
239 .SA(ISA),
240 .BA(IBA),
241 .CS_N(ICS_N),
242 .CKE(ICKE),
243 .RAS_N(IRAS_N),
244 .CAS_N(ICAS_N),
245 .WE_N(IWE_N)
246 );
247
248 sdr_data_path data_path1(
249 .CLK(CLK),
250 .RESET_N(RESET_N),
251 .DATAIN(mDATAIN),
252 .DM( 2 ' b00),
253 .DQOUT(DQOUT),
254 .DQM(IDQM)
255 );
256
257 Sdram_FIFO write_fifo1 (
258 .data(WR1_DATA),
259 .wrreq(WR1),
260 .wrclk(WR1_CLK),
261 .aclr(WR1_LOAD),
262 .rdreq(IN_REQ & WR_MASK[ 0 ]),
263 .rdclk(CLK),
264 .q(mDATAIN1),
265 .wrfull(WR1_FULL),
266 .wrusedw(WR1_USE),
267 .rdusedw(write_side_fifo_rusedw1)
268 );
269
270 Sdram_FIFO write_fifo2(
271 .data(WR2_DATA),
272 .wrreq(WR2),
273 .wrclk(WR2_CLK),
274 .aclr(WR2_LOAD),
275 .rdreq(IN_REQ & WR_MASK[ 1 ]),
276 .rdclk(CLK),
277 .q(mDATAIN2),
278 .wrfull(WR2_FULL),
279 .wrusedw(WR2_USE),
280 .rdusedw(write_side_fifo_rusedw2)
281 );
282
283 assign mDATAIN = (WR_MASK[ 0 ]) ? mDATAIN1 : mDATAIN2;
284
285 Sdram_FIFO read_fifo1 (
286 .data(mDATAOUT),
287 .wrreq(OUT_VALID & RD_MASK[ 0 ]),
288 .wrclk(CLK),
289 .aclr(RD1_LOAD),
290 .rdreq(RD1),
291 .rdclk(RD1_CLK),
292 .q(RD1_DATA),
293 .wrusedw(read_side_fifo_wusedw1),
294 .rdempty(RD1_EMPTY),
295 .rdusedw(RD1_USE)
296 );
297
298 Sdram_FIFO read_fifo2 (
299 .data(mDATAOUT),
300 .wrreq(OUT_VALID & RD_MASK[ 1 ]),
301 .wrclk(CLK),
302 .aclr(RD2_LOAD),
303 .rdreq(RD2),
304 .rdclk(RD2_CLK),
305 .q(RD2_DATA),
306 .wrusedw(read_side_fifo_wusedw2),
307 .rdempty(RD2_EMPTY),
308 .rdusedw(RD2_USE)
309 );
310
311 always@(posedge CLK)
312 begin
313 SA <= (ST == SC_CL + mLENGTH) ? 12 ' h200 : ISA;
314 BA <= IBA;
315 CS_N <= ICS_N;
316 CKE <= ICKE;
317 RAS_N <= (ST == SC_CL + mLENGTH) ? 1 ' b0 : IRAS_N;
318 CAS_N <= (ST == SC_CL + mLENGTH) ? 1 ' b1 : ICAS_N;
319 WE_N <= (ST == SC_CL + mLENGTH) ? 1 ' b0 : IWE_N;
320 PM_STOP <= (ST == SC_CL + mLENGTH) ? 1 ' b1 : 1 ' b0;
321 PM_DONE <= (ST == SC_CL + SC_RCD + mLENGTH + 2 ) ? 1 ' b1 : 1 ' b0;
322 DQM <= ( active && (ST >= SC_CL) ) ? (((ST == SC_CL + mLENGTH) && Write) ? 2 ' b11 : 2 ' b00 ) : 2 ' b11;
323 mDATAOUT <= DQ;
324 end
325
326 assign DQ = oe ? DQOUT : `DSIZE ' hzzzz;
327 assign active = Read | Write;
328
329 always@(posedge CLK or negedge RESET_N)
330 begin
331 if (RESET_N == 0 )
332 begin
333 CMD <= 0 ;
334 ST <= 0 ;
335 Pre_RD <= 0 ;
336 Pre_WR <= 0 ;
337 Read <= 0 ;
338 Write <= 0 ;
339 OUT_VALID <= 0 ;
340 IN_REQ <= 0 ;
341 mWR_DONE <= 0 ;
342 mRD_DONE <= 0 ;
343 end
344 else
345 begin
346 Pre_RD <= mRD;
347 Pre_WR <= mWR;
348 case (ST)
349 0 :
350 begin
351 if ({Pre_RD,mRD} == 2 ' b01)
352 begin
353 Read <= 1 ;
354 Write <= 0 ;
355 CMD <= 2 ' b01;
356 ST <= 1 ;
357 end
358 else if ({Pre_WR,mWR} == 2 ' b01)
359 begin
360 Read <= 0 ;
361 Write <= 1 ;
362 CMD <= 2 ' b10;
363 ST <= 1 ;
364 end
365 end
366 1 :
367 begin
368 if (CMDACK == 1 )
369 begin
370 CMD <= 2 ' b00;
371 ST <= 2 ;
372 end
373 end
374 default :
375 begin
376 if (ST != SC_CL + SC_RCD + mLENGTH + 1 )
377 ST <= ST + 1 ;
378 else
379 ST <= 0 ;
380 end
381 endcase
382
383 if (Read)
384 begin
385 if (ST == SC_CL + SC_RCD + 1 )
386 OUT_VALID <= 1 ;
387 else if (ST == SC_CL + SC_RCD + mLENGTH + 1 )
388 begin
389 OUT_VALID <= 0 ;
390 Read <= 0 ;
391 mRD_DONE <= 1 ;
392 end
393 end
394 else
395 mRD_DONE <= 0 ;
396
397 if (Write)
398 begin
399 if (ST == SC_CL - 1 )
400 IN_REQ <= 1 ;
401 else if (ST == SC_CL + mLENGTH - 1 )
402 IN_REQ <= 0 ;
403 else if (ST == SC_CL + SC_RCD + mLENGTH)
404 begin
405 Write <= 0 ;
406 mWR_DONE <= 1 ;
407 end
408 end
409 else
410 mWR_DONE <= 0 ;
411 end
412 end
413 // Internal Address & Length Control
414 always@(posedge CLK or negedge RESET_N)
415 begin
416 if ( ! RESET_N)
417 begin
418 rWR1_ADDR <= 0 ;
419 rWR2_ADDR <= 22 ' h100000;
420 rRD1_ADDR <= 320 * 8 ;
421 rRD2_ADDR <= 22 ' h100000+320*8;
422 rWR1_MAX_ADDR <= 320 * 256 ;
423 rWR2_MAX_ADDR <= 22 ' h100000+320*256;
424 rRD1_MAX_ADDR <= 320 * 248 ;
425 rRD2_MAX_ADDR <= 22 ' h100000+320*248;
426 rWR1_LENGTH <= 256 ;
427 rWR2_LENGTH <= 256 ;
428 rRD1_LENGTH <= 256 ;
429 rRD2_LENGTH <= 256 ;
430 end
431 else
432 begin
433 // Write Side 1
434 if (WR1_LOAD)
435 begin
436 rWR1_ADDR <= WR1_ADDR;
437 rWR1_LENGTH <= WR1_LENGTH;
438 end
439 else if (mWR_DONE & WR_MASK[ 0 ])
440 begin
441 if (rWR1_ADDR < rWR1_MAX_ADDR - rWR1_LENGTH)
442 rWR1_ADDR <= rWR1_ADDR + rWR1_LENGTH;
443 else
444 rWR1_ADDR <= WR1_ADDR;
445 end
446
447 // Write Side 2
448 if (WR2_LOAD)
449 begin
450 rWR2_ADDR <= WR2_ADDR;
451 rWR2_LENGTH <= WR2_LENGTH;
452 end
453 else if (mWR_DONE & WR_MASK[ 1 ])
454 begin
455 if (rWR2_ADDR < rWR2_MAX_ADDR - rWR2_LENGTH)
456 rWR2_ADDR <= rWR2_ADDR + rWR2_LENGTH;
457 else
458 rWR2_ADDR <= WR2_ADDR;
459 end
460
461 // Read Side 1
462 if (RD1_LOAD)
463 begin
464 rRD1_ADDR <= RD1_ADDR;
465 rRD1_LENGTH <= RD1_LENGTH;
466 end
467 else if (mRD_DONE & RD_MASK[ 0 ])
468 begin
469 if (rRD1_ADDR < rRD1_MAX_ADDR - rRD1_LENGTH)
470 rRD1_ADDR <= rRD1_ADDR + rRD1_LENGTH;
471 else
472 rRD1_ADDR <= RD1_ADDR;
473 end
474
475 // Read Side 2
476 if (RD2_LOAD)
477 begin
478 rRD2_ADDR <= RD2_ADDR;
479 rRD2_LENGTH <= RD2_LENGTH;
480 end
481 else if (mRD_DONE & RD_MASK[ 1 ])
482 begin
483 if (rRD2_ADDR < rRD2_MAX_ADDR - rRD2_LENGTH)
484 rRD2_ADDR <= rRD2_ADDR + rRD2_LENGTH;
485 else
486 rRD2_ADDR <= RD2_ADDR;
487 end
488 end
489 end
490
491 // Auto Read/Write Control
492 always@(posedge CLK or negedge RESET_N)
493 begin
494 if ( ! RESET_N)
495 begin
496 mWR <= 0 ;
497 mRD <= 0 ;
498 mADDR <= 0 ;
499 mLENGTH <= 0 ;
500 end
501 else
502 begin
503 if ((mWR == 0 ) && (mRD == 0 ) && (ST == 0 ) &&
504 (WR_MASK == 0 ) && (RD_MASK == 0 ) &&
505 (WR1_LOAD == 0 ) && (RD1_LOAD == 0 ) &&
506 (WR2_LOAD == 0 ) && (RD2_LOAD == 0 ))
507 begin
508 // Write Side 1
509 if ( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH != 0 ) )
510 begin
511 mADDR <= rWR1_ADDR;
512 mLENGTH <= rWR1_LENGTH;
513 WR_MASK <= 2 ' b01;
514 RD_MASK <= 2 ' b00;
515 mWR <= 1 ;
516 mRD <= 0 ;
517 end
518 // Write Side 2
519 else if ( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH != 0 ) )
520 begin
521 mADDR <= rWR2_ADDR;
522 mLENGTH <= rWR2_LENGTH;
523 WR_MASK <= 2 ' b10;
524 RD_MASK <= 2 ' b00;
525 mWR <= 1 ;
526 mRD <= 0 ;
527 end
528 // Read Side 1
529 else if ( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
530 begin
531 mADDR <= rRD1_ADDR;
532 mLENGTH <= rRD1_LENGTH;
533 WR_MASK <= 2 ' b00;
534 RD_MASK <= 2 ' b01;
535 mWR <= 0 ;
536 mRD <= 1 ;
537 end
538 // Read Side 2
539 else if ( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
540 begin
541 mADDR <= rRD2_ADDR;
542 mLENGTH <= rRD2_LENGTH;
543 WR_MASK <= 2 ' b00;
544 RD_MASK <= 2 ' b10;
545 mWR <= 0 ;
546 mRD <= 1 ;
547 end
548 end
549
550 if (mWR_DONE)
551 begin
552 WR_MASK <= 0 ;
553 mWR <= 0 ;
554 end
555
556 if (mRD_DONE)
557 begin
558 RD_MASK <= 0 ;
559 mRD <= 0 ;
560 end
561 end
562 end
563
564 endmodule
2 // HOST Side
3 REF_CLK,
4 RESET_N,
5 // FIFO Write Side 1
6 WR1_DATA,
7 WR1,
8 WR1_ADDR,
9 WR1_MAX_ADDR,
10 WR1_LENGTH,
11 WR1_LOAD,
12 WR1_CLK,
13 WR1_FULL,
14 WR1_USE,
15 // FIFO Write Side 2
16 WR2_DATA,
17 WR2,
18 WR2_ADDR,
19 WR2_MAX_ADDR,
20 WR2_LENGTH,
21 WR2_LOAD,
22 WR2_CLK,
23 WR2_FULL,
24 WR2_USE,
25 // FIFO Read Side 1
26 RD1_DATA,
27 RD1,
28 RD1_ADDR,
29 RD1_MAX_ADDR,
30 RD1_LENGTH,
31 RD1_LOAD,
32 RD1_CLK,
33 RD1_EMPTY,
34 RD1_USE,
35 // FIFO Read Side 2
36 RD2_DATA,
37 RD2,
38 RD2_ADDR,
39 RD2_MAX_ADDR,
40 RD2_LENGTH,
41 RD2_LOAD,
42 RD2_CLK,
43 RD2_EMPTY,
44 RD2_USE,
45 // SDRAM Side
46 SA,
47 BA,
48 CS_N,
49 CKE,
50 RAS_N,
51 CAS_N,
52 WE_N,
53 DQ,
54 DQM,
55 SDR_CLK
56 );
57
58 `include " Sdram_Params.h "
59 // HOST Side
60 input REF_CLK; // System Clock
61 input RESET_N; // System Reset
62
63 // FIFO Write Side 1
64 input [`DSIZE - 1 : 0 ] WR1_DATA; // Data input
65 input WR1; // Write Request
66 input [`ASIZE - 1 : 0 ] WR1_ADDR; // Write start address
67 input [`ASIZE - 1 : 0 ] WR1_MAX_ADDR; // Write max address
68 input [ 8 : 0 ] WR1_LENGTH; // Write length
69 input WR1_LOAD; // Write register load & fifo clear
70 input WR1_CLK; // Write fifo clock
71 output WR1_FULL; // Write fifo full
72 output [ 8 : 0 ] WR1_USE; // Write fifo usedw
73
74 // FIFO Write Side 2
75 input [`DSIZE - 1 : 0 ] WR2_DATA; // Data input
76 input WR2; // Write Request
77 input [`ASIZE - 1 : 0 ] WR2_ADDR; // Write start address
78 input [`ASIZE - 1 : 0 ] WR2_MAX_ADDR; // Write max address
79 input [ 8 : 0 ] WR2_LENGTH; // Write length
80 input WR2_LOAD; // Write register load & fifo clear
81 input WR2_CLK; // Write fifo clock
82 output WR2_FULL; // Write fifo full
83 output [ 8 : 0 ] WR2_USE; // Write fifo usedw
84
85 // FIFO Read Side 1
86 output [`DSIZE - 1 : 0 ] RD1_DATA; // Data output
87 input RD1; // Read Request
88 input [`ASIZE - 1 : 0 ] RD1_ADDR; // Read start address
89 input [`ASIZE - 1 : 0 ] RD1_MAX_ADDR; // Read max address
90 input [ 8 : 0 ] RD1_LENGTH; // Read length
91 input RD1_LOAD; // Read register load & fifo clear
92 input RD1_CLK; // Read fifo clock
93 output RD1_EMPTY; // Read fifo empty
94 output [ 8 : 0 ] RD1_USE; // Read fifo usedw
95
96 // FIFO Read Side 2
97 output [`DSIZE - 1 : 0 ] RD2_DATA; // Data output
98 input RD2; // Read Request
99 input [`ASIZE - 1 : 0 ] RD2_ADDR; // Read start address
100 input [`ASIZE - 1 : 0 ] RD2_MAX_ADDR; // Read max address
101 input [ 8 : 0 ] RD2_LENGTH; // Read length
102 input RD2_LOAD; // Read register load & fifo clear
103 input RD2_CLK; // Read fifo clock
104 output RD2_EMPTY; // Read fifo empty
105 output [ 8 : 0 ] RD2_USE; // Read fifo usedw
106
107 // SDRAM Side
108 output [ 11 : 0 ] SA; // SDRAM address output
109 output [ 1 : 0 ] BA; // SDRAM bank address
110 output [ 1 : 0 ] CS_N; // SDRAM Chip Selects
111 output CKE; // SDRAM clock enable
112 output RAS_N; // SDRAM Row address Strobe
113 output CAS_N; // SDRAM Column address Strobe
114 output WE_N; // SDRAM write enable
115 inout [`DSIZE - 1 : 0 ] DQ; // SDRAM data bus
116 output [`DSIZE / 8 - 1 : 0 ] DQM; // SDRAM data mask lines
117 output SDR_CLK; // SDRAM clock
118
119 // Internal Registers/Wires
120 // Controller
121 reg [`ASIZE - 1 : 0 ] mADDR; // Internal address
122 reg [ 8 : 0 ] mLENGTH; // Internal length
123 reg [`ASIZE - 1 : 0 ] rWR1_ADDR; // Register write address
124 reg [`ASIZE - 1 : 0 ] rWR1_MAX_ADDR; // Register max write address
125 reg [ 8 : 0 ] rWR1_LENGTH; // Register write length
126 reg [`ASIZE - 1 : 0 ] rWR2_ADDR; // Register write address
127 reg [`ASIZE - 1 : 0 ] rWR2_MAX_ADDR; // Register max write address
128 reg [ 8 : 0 ] rWR2_LENGTH; // Register write length
129 reg [`ASIZE - 1 : 0 ] rRD1_ADDR; // Register read address
130 reg [`ASIZE - 1 : 0 ] rRD1_MAX_ADDR; // Register max read address
131 reg [ 8 : 0 ] rRD1_LENGTH; // Register read length
132 reg [`ASIZE - 1 : 0 ] rRD2_ADDR; // Register read address
133 reg [`ASIZE - 1 : 0 ] rRD2_MAX_ADDR; // Register max read address
134 reg [ 8 : 0 ] rRD2_LENGTH; // Register read length
135 reg [ 1 : 0 ] WR_MASK; // Write port active mask
136 reg [ 1 : 0 ] RD_MASK; // Read port active mask
137 reg mWR_DONE; // Flag write done, 1 pulse SDR_CLK
138 reg mRD_DONE; // Flag read done, 1 pulse SDR_CLK
139 reg mWR,Pre_WR; // Internal WR edge capture
140 reg mRD,Pre_RD; // Internal RD edge capture
141 reg [ 9 : 0 ] ST; // Controller status
142 reg [ 1 : 0 ] CMD; // Controller command
143 reg PM_STOP; // Flag page mode stop
144 reg PM_DONE; // Flag page mode done
145 reg Read; // Flag read active
146 reg Write; // Flag write active
147 reg [`DSIZE - 1 : 0 ] mDATAOUT; // Controller Data output
148 wire [`DSIZE - 1 : 0 ] mDATAIN; // Controller Data input
149 wire [`DSIZE - 1 : 0 ] mDATAIN1; // Controller Data input 1
150 wire [`DSIZE - 1 : 0 ] mDATAIN2; // Controller Data input 2
151 wire CMDACK; // Controller command acknowledgement
152
153 // DRAM Control
154 reg [`DSIZE / 8 - 1 : 0 ] DQM; // SDRAM data mask lines
155 reg [ 11 : 0 ] SA; // SDRAM address output
156 reg [ 1 : 0 ] BA; // SDRAM bank address
157 reg [ 1 : 0 ] CS_N; // SDRAM Chip Selects
158 reg CKE; // SDRAM clock enable
159 reg RAS_N; // SDRAM Row address Strobe
160 reg CAS_N; // SDRAM Column address Strobe
161 reg WE_N; // SDRAM write enable
162 wire [`DSIZE - 1 : 0 ] DQOUT; // SDRAM data out link
163 wire [`DSIZE / 8 - 1 : 0 ] IDQM; // SDRAM data mask lines
164 wire [ 11 : 0 ] ISA; // SDRAM address output
165 wire [ 1 : 0 ] IBA; // SDRAM bank address
166 wire [ 1 : 0 ] ICS_N; // SDRAM Chip Selects
167 wire ICKE; // SDRAM clock enable
168 wire IRAS_N; // SDRAM Row address Strobe
169 wire ICAS_N; // SDRAM Column address Strobe
170 wire IWE_N; // SDRAM write enable
171
172 // FIFO Control
173 reg OUT_VALID; // Output data request to read side fifo
174 reg IN_REQ; // Input data request to write side fifo
175 wire [ 8 : 0 ] write_side_fifo_rusedw1;
176 wire [ 8 : 0 ] read_side_fifo_wusedw1;
177 wire [ 8 : 0 ] write_side_fifo_rusedw2;
178 wire [ 8 : 0 ] read_side_fifo_wusedw2;
179
180 // DRAM Internal Control
181 wire [`ASIZE - 1 : 0 ] saddr;
182 wire load_mode;
183 wire nop;
184 wire reada;
185 wire writea;
186 wire refresh;
187 wire precharge;
188 wire oe;
189 wire ref_ack;
190 wire ref_req;
191 wire init_req;
192 wire cm_ack;
193 wire active;
194 wire CLK;
195
196
197 Sdram_PLL sdram_pll1 (
198 .inclk0(REF_CLK),
199 .c0(CLK),
200 .c1(SDR_CLK)
201 );
202
203 control_interface control1 (
204 .CLK(CLK),
205 .RESET_N(RESET_N),
206 .CMD(CMD),
207 .ADDR(mADDR),
208 .REF_ACK(ref_ack),
209 .CM_ACK(cm_ack),
210 .NOP(nop),
211 .READA(reada),
212 .WRITEA(writea),
213 .REFRESH(refresh),
214 .PRECHARGE(precharge),
215 .LOAD_MODE(load_mode),
216 .SADDR(saddr),
217 .REF_REQ(ref_req),
218 .INIT_REQ(init_req),
219 .CMD_ACK(CMDACK)
220 );
221
222 command command1(
223 .CLK(CLK),
224 .RESET_N(RESET_N),
225 .SADDR(saddr),
226 .NOP(nop),
227 .READA(reada),
228 .WRITEA(writea),
229 .REFRESH(refresh),
230 .LOAD_MODE(load_mode),
231 .PRECHARGE(precharge),
232 .REF_REQ(ref_req),
233 .INIT_REQ(init_req),
234 .REF_ACK(ref_ack),
235 .CM_ACK(cm_ack),
236 .OE(oe),
237 .PM_STOP(PM_STOP),
238 .PM_DONE(PM_DONE),
239 .SA(ISA),
240 .BA(IBA),
241 .CS_N(ICS_N),
242 .CKE(ICKE),
243 .RAS_N(IRAS_N),
244 .CAS_N(ICAS_N),
245 .WE_N(IWE_N)
246 );
247
248 sdr_data_path data_path1(
249 .CLK(CLK),
250 .RESET_N(RESET_N),
251 .DATAIN(mDATAIN),
252 .DM( 2 ' b00),
253 .DQOUT(DQOUT),
254 .DQM(IDQM)
255 );
256
257 Sdram_FIFO write_fifo1 (
258 .data(WR1_DATA),
259 .wrreq(WR1),
260 .wrclk(WR1_CLK),
261 .aclr(WR1_LOAD),
262 .rdreq(IN_REQ & WR_MASK[ 0 ]),
263 .rdclk(CLK),
264 .q(mDATAIN1),
265 .wrfull(WR1_FULL),
266 .wrusedw(WR1_USE),
267 .rdusedw(write_side_fifo_rusedw1)
268 );
269
270 Sdram_FIFO write_fifo2(
271 .data(WR2_DATA),
272 .wrreq(WR2),
273 .wrclk(WR2_CLK),
274 .aclr(WR2_LOAD),
275 .rdreq(IN_REQ & WR_MASK[ 1 ]),
276 .rdclk(CLK),
277 .q(mDATAIN2),
278 .wrfull(WR2_FULL),
279 .wrusedw(WR2_USE),
280 .rdusedw(write_side_fifo_rusedw2)
281 );
282
283 assign mDATAIN = (WR_MASK[ 0 ]) ? mDATAIN1 : mDATAIN2;
284
285 Sdram_FIFO read_fifo1 (
286 .data(mDATAOUT),
287 .wrreq(OUT_VALID & RD_MASK[ 0 ]),
288 .wrclk(CLK),
289 .aclr(RD1_LOAD),
290 .rdreq(RD1),
291 .rdclk(RD1_CLK),
292 .q(RD1_DATA),
293 .wrusedw(read_side_fifo_wusedw1),
294 .rdempty(RD1_EMPTY),
295 .rdusedw(RD1_USE)
296 );
297
298 Sdram_FIFO read_fifo2 (
299 .data(mDATAOUT),
300 .wrreq(OUT_VALID & RD_MASK[ 1 ]),
301 .wrclk(CLK),
302 .aclr(RD2_LOAD),
303 .rdreq(RD2),
304 .rdclk(RD2_CLK),
305 .q(RD2_DATA),
306 .wrusedw(read_side_fifo_wusedw2),
307 .rdempty(RD2_EMPTY),
308 .rdusedw(RD2_USE)
309 );
310
311 always@(posedge CLK)
312 begin
313 SA <= (ST == SC_CL + mLENGTH) ? 12 ' h200 : ISA;
314 BA <= IBA;
315 CS_N <= ICS_N;
316 CKE <= ICKE;
317 RAS_N <= (ST == SC_CL + mLENGTH) ? 1 ' b0 : IRAS_N;
318 CAS_N <= (ST == SC_CL + mLENGTH) ? 1 ' b1 : ICAS_N;
319 WE_N <= (ST == SC_CL + mLENGTH) ? 1 ' b0 : IWE_N;
320 PM_STOP <= (ST == SC_CL + mLENGTH) ? 1 ' b1 : 1 ' b0;
321 PM_DONE <= (ST == SC_CL + SC_RCD + mLENGTH + 2 ) ? 1 ' b1 : 1 ' b0;
322 DQM <= ( active && (ST >= SC_CL) ) ? (((ST == SC_CL + mLENGTH) && Write) ? 2 ' b11 : 2 ' b00 ) : 2 ' b11;
323 mDATAOUT <= DQ;
324 end
325
326 assign DQ = oe ? DQOUT : `DSIZE ' hzzzz;
327 assign active = Read | Write;
328
329 always@(posedge CLK or negedge RESET_N)
330 begin
331 if (RESET_N == 0 )
332 begin
333 CMD <= 0 ;
334 ST <= 0 ;
335 Pre_RD <= 0 ;
336 Pre_WR <= 0 ;
337 Read <= 0 ;
338 Write <= 0 ;
339 OUT_VALID <= 0 ;
340 IN_REQ <= 0 ;
341 mWR_DONE <= 0 ;
342 mRD_DONE <= 0 ;
343 end
344 else
345 begin
346 Pre_RD <= mRD;
347 Pre_WR <= mWR;
348 case (ST)
349 0 :
350 begin
351 if ({Pre_RD,mRD} == 2 ' b01)
352 begin
353 Read <= 1 ;
354 Write <= 0 ;
355 CMD <= 2 ' b01;
356 ST <= 1 ;
357 end
358 else if ({Pre_WR,mWR} == 2 ' b01)
359 begin
360 Read <= 0 ;
361 Write <= 1 ;
362 CMD <= 2 ' b10;
363 ST <= 1 ;
364 end
365 end
366 1 :
367 begin
368 if (CMDACK == 1 )
369 begin
370 CMD <= 2 ' b00;
371 ST <= 2 ;
372 end
373 end
374 default :
375 begin
376 if (ST != SC_CL + SC_RCD + mLENGTH + 1 )
377 ST <= ST + 1 ;
378 else
379 ST <= 0 ;
380 end
381 endcase
382
383 if (Read)
384 begin
385 if (ST == SC_CL + SC_RCD + 1 )
386 OUT_VALID <= 1 ;
387 else if (ST == SC_CL + SC_RCD + mLENGTH + 1 )
388 begin
389 OUT_VALID <= 0 ;
390 Read <= 0 ;
391 mRD_DONE <= 1 ;
392 end
393 end
394 else
395 mRD_DONE <= 0 ;
396
397 if (Write)
398 begin
399 if (ST == SC_CL - 1 )
400 IN_REQ <= 1 ;
401 else if (ST == SC_CL + mLENGTH - 1 )
402 IN_REQ <= 0 ;
403 else if (ST == SC_CL + SC_RCD + mLENGTH)
404 begin
405 Write <= 0 ;
406 mWR_DONE <= 1 ;
407 end
408 end
409 else
410 mWR_DONE <= 0 ;
411 end
412 end
413 // Internal Address & Length Control
414 always@(posedge CLK or negedge RESET_N)
415 begin
416 if ( ! RESET_N)
417 begin
418 rWR1_ADDR <= 0 ;
419 rWR2_ADDR <= 22 ' h100000;
420 rRD1_ADDR <= 320 * 8 ;
421 rRD2_ADDR <= 22 ' h100000+320*8;
422 rWR1_MAX_ADDR <= 320 * 256 ;
423 rWR2_MAX_ADDR <= 22 ' h100000+320*256;
424 rRD1_MAX_ADDR <= 320 * 248 ;
425 rRD2_MAX_ADDR <= 22 ' h100000+320*248;
426 rWR1_LENGTH <= 256 ;
427 rWR2_LENGTH <= 256 ;
428 rRD1_LENGTH <= 256 ;
429 rRD2_LENGTH <= 256 ;
430 end
431 else
432 begin
433 // Write Side 1
434 if (WR1_LOAD)
435 begin
436 rWR1_ADDR <= WR1_ADDR;
437 rWR1_LENGTH <= WR1_LENGTH;
438 end
439 else if (mWR_DONE & WR_MASK[ 0 ])
440 begin
441 if (rWR1_ADDR < rWR1_MAX_ADDR - rWR1_LENGTH)
442 rWR1_ADDR <= rWR1_ADDR + rWR1_LENGTH;
443 else
444 rWR1_ADDR <= WR1_ADDR;
445 end
446
447 // Write Side 2
448 if (WR2_LOAD)
449 begin
450 rWR2_ADDR <= WR2_ADDR;
451 rWR2_LENGTH <= WR2_LENGTH;
452 end
453 else if (mWR_DONE & WR_MASK[ 1 ])
454 begin
455 if (rWR2_ADDR < rWR2_MAX_ADDR - rWR2_LENGTH)
456 rWR2_ADDR <= rWR2_ADDR + rWR2_LENGTH;
457 else
458 rWR2_ADDR <= WR2_ADDR;
459 end
460
461 // Read Side 1
462 if (RD1_LOAD)
463 begin
464 rRD1_ADDR <= RD1_ADDR;
465 rRD1_LENGTH <= RD1_LENGTH;
466 end
467 else if (mRD_DONE & RD_MASK[ 0 ])
468 begin
469 if (rRD1_ADDR < rRD1_MAX_ADDR - rRD1_LENGTH)
470 rRD1_ADDR <= rRD1_ADDR + rRD1_LENGTH;
471 else
472 rRD1_ADDR <= RD1_ADDR;
473 end
474
475 // Read Side 2
476 if (RD2_LOAD)
477 begin
478 rRD2_ADDR <= RD2_ADDR;
479 rRD2_LENGTH <= RD2_LENGTH;
480 end
481 else if (mRD_DONE & RD_MASK[ 1 ])
482 begin
483 if (rRD2_ADDR < rRD2_MAX_ADDR - rRD2_LENGTH)
484 rRD2_ADDR <= rRD2_ADDR + rRD2_LENGTH;
485 else
486 rRD2_ADDR <= RD2_ADDR;
487 end
488 end
489 end
490
491 // Auto Read/Write Control
492 always@(posedge CLK or negedge RESET_N)
493 begin
494 if ( ! RESET_N)
495 begin
496 mWR <= 0 ;
497 mRD <= 0 ;
498 mADDR <= 0 ;
499 mLENGTH <= 0 ;
500 end
501 else
502 begin
503 if ((mWR == 0 ) && (mRD == 0 ) && (ST == 0 ) &&
504 (WR_MASK == 0 ) && (RD_MASK == 0 ) &&
505 (WR1_LOAD == 0 ) && (RD1_LOAD == 0 ) &&
506 (WR2_LOAD == 0 ) && (RD2_LOAD == 0 ))
507 begin
508 // Write Side 1
509 if ( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH != 0 ) )
510 begin
511 mADDR <= rWR1_ADDR;
512 mLENGTH <= rWR1_LENGTH;
513 WR_MASK <= 2 ' b01;
514 RD_MASK <= 2 ' b00;
515 mWR <= 1 ;
516 mRD <= 0 ;
517 end
518 // Write Side 2
519 else if ( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH != 0 ) )
520 begin
521 mADDR <= rWR2_ADDR;
522 mLENGTH <= rWR2_LENGTH;
523 WR_MASK <= 2 ' b10;
524 RD_MASK <= 2 ' b00;
525 mWR <= 1 ;
526 mRD <= 0 ;
527 end
528 // Read Side 1
529 else if ( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
530 begin
531 mADDR <= rRD1_ADDR;
532 mLENGTH <= rRD1_LENGTH;
533 WR_MASK <= 2 ' b00;
534 RD_MASK <= 2 ' b01;
535 mWR <= 0 ;
536 mRD <= 1 ;
537 end
538 // Read Side 2
539 else if ( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
540 begin
541 mADDR <= rRD2_ADDR;
542 mLENGTH <= rRD2_LENGTH;
543 WR_MASK <= 2 ' b00;
544 RD_MASK <= 2 ' b10;
545 mWR <= 0 ;
546 mRD <= 1 ;
547 end
548 end
549
550 if (mWR_DONE)
551 begin
552 WR_MASK <= 0 ;
553 mWR <= 0 ;
554 end
555
556 if (mRD_DONE)
557 begin
558 RD_MASK <= 0 ;
559 mRD <= 0 ;
560 end
561 end
562 end
563
564 endmodule
LCM_Controller.v
1
module LCM_Controller (
2 // Host Side
3 iRed,
4 iGreen,
5 iBlue,
6 // LCM Side
7 LCM_DATA,
8 LCM_VSYNC,
9 LCM_HSYNC,
10 LCM_DCLK,
11 LCM_GRST,
12 LCM_SHDB,
13 // Control Signals
14 oDATA_REQ,
15 iCLK,
16 iRST_N
17 );
18
19 // Host Side
20 input [ 7 : 0 ] iRed;
21 input [ 7 : 0 ] iGreen;
22 input [ 7 : 0 ] iBlue;
23 // LCM Side
24 output [ 7 : 0 ] LCM_DATA;
25 output LCM_VSYNC;
26 output LCM_HSYNC;
27 output LCM_DCLK;
28 output LCM_GRST;
29 output LCM_SHDB;
30
31 // Control Signals
32 output oDATA_REQ;
33 input iCLK;
34 input iRST_N;
35 // Internal Register and Wire
36 reg [ 10 : 0 ] H_Cont;
37 reg [ 10 : 0 ] V_Cont;
38 reg mVGA_H_SYNC;
39 reg mVGA_V_SYNC;
40 reg mDATA_REQ;
41 reg [ 1 : 0 ] MOD_3;
42 reg [ 1 : 0 ] Pre_MOD_3;
43
44 // Horizontal Parameter ( Pixel )
45 parameter H_SYNC_CYC = 1 ;
46 parameter H_SYNC_BACK = 151 ;
47 parameter H_SYNC_ACT = 960 ;
48 parameter H_SYNC_FRONT = 59 ;
49 parameter H_SYNC_TOTAL = 1171 ;
50
51 // Virtical Parameter ( Line )
52 parameter V_SYNC_CYC = 1 ;
53 parameter V_SYNC_BACK = 13 ;
54 parameter V_SYNC_ACT = 240 ;
55 parameter V_SYNC_FRONT = 8 ;
56 parameter V_SYNC_TOTAL = 262 ;
57
58 assign LCM_SHDB = 1 ' b1;
59 assign LCM_GRST = 1 ' b1;
60 assign LCM_DCLK = ~ iCLK;
61 assign LCM_VSYNC = mVGA_V_SYNC;
62 assign LCM_HSYNC = mVGA_H_SYNC;
63 assign LCM_DATA = (MOD_3 == 2 ' h00) ? iRed :
64 (MOD_3 == 2 ' h01) ? iGreen :
65 iBlue;
66 assign oDATA_REQ = mDATA_REQ;
67
68 always@(posedge iCLK or negedge iRST_N)
69 begin
70 if ( ! iRST_N)
71 begin
72 MOD_3 <= 2 ' b00;
73 Pre_MOD_3 <= 2 ' b00;
74 mDATA_REQ <= 1 ' b0;
75 end
76 else
77 begin
78 Pre_MOD_3 <= MOD_3;
79 if (H_Cont > H_SYNC_BACK - 2 && H_Cont < (H_SYNC_TOTAL - H_SYNC_FRONT - 2 ) &&
80 V_Cont > V_SYNC_BACK + 1 && V_Cont < (V_SYNC_TOTAL - V_SYNC_FRONT + 1 ))
81 begin
82 if (MOD_3 < 2 ' b10)
83 MOD_3 <= MOD_3 + 1 ' b1;
84 else
85 MOD_3 <= 2 ' b00;
86
87 if ((MOD_3 == 2 ' b01) && (Pre_MOD_3==2 ' b00))
88 mDATA_REQ <= 1 ' b1;
89 else
90 mDATA_REQ <= 1 ' b0;
91 end
92 else
93 begin
94 MOD_3 <= 2 ' b00;
95 mDATA_REQ <= 1 ' b0;
96 end
97 end
98 end
99
100 // H_Sync Generator, Ref. 18.42 MHz Clock
101 always@(posedge iCLK or negedge iRST_N)
102 begin
103 if ( ! iRST_N)
104 begin
105 H_Cont <= 0 ;
106 mVGA_H_SYNC <= 0 ;
107 end
108 else
109 begin
110 // H_Sync Counter
111 if (H_Cont < H_SYNC_TOTAL)
112 H_Cont <= H_Cont + 1 ;
113 else
114 H_Cont <= 0 ;
115
116 // H_Sync Generator
117 if (H_Cont < H_SYNC_CYC)
118 mVGA_H_SYNC <= 0 ;
119 else
120 mVGA_H_SYNC <= 1 ;
121 end
122 end
123
124 // V_Sync Generator, Ref. H_Sync
125 always@(posedge iCLK or negedge iRST_N)
126 begin
127 if ( ! iRST_N)
128 begin
129 V_Cont <= 0 ;
130 mVGA_V_SYNC <= 0 ;
131 end
132 else
133 begin
134 // When H_Sync Re-start
135 if (H_Cont == 0 )
136 begin
137 // V_Sync Counter
138 if (V_Cont < V_SYNC_TOTAL)
139 V_Cont <= V_Cont + 1 ;
140 else
141 V_Cont <= 0 ;
142
143 // V_Sync Generator
144 if (V_Cont < V_SYNC_CYC)
145 mVGA_V_SYNC <= 0 ;
146 else
147 mVGA_V_SYNC <= 1 ;
148 end
149 end
150 end
151
152 endmodule
2 // Host Side
3 iRed,
4 iGreen,
5 iBlue,
6 // LCM Side
7 LCM_DATA,
8 LCM_VSYNC,
9 LCM_HSYNC,
10 LCM_DCLK,
11 LCM_GRST,
12 LCM_SHDB,
13 // Control Signals
14 oDATA_REQ,
15 iCLK,
16 iRST_N
17 );
18
19 // Host Side
20 input [ 7 : 0 ] iRed;
21 input [ 7 : 0 ] iGreen;
22 input [ 7 : 0 ] iBlue;
23 // LCM Side
24 output [ 7 : 0 ] LCM_DATA;
25 output LCM_VSYNC;
26 output LCM_HSYNC;
27 output LCM_DCLK;
28 output LCM_GRST;
29 output LCM_SHDB;
30
31 // Control Signals
32 output oDATA_REQ;
33 input iCLK;
34 input iRST_N;
35 // Internal Register and Wire
36 reg [ 10 : 0 ] H_Cont;
37 reg [ 10 : 0 ] V_Cont;
38 reg mVGA_H_SYNC;
39 reg mVGA_V_SYNC;
40 reg mDATA_REQ;
41 reg [ 1 : 0 ] MOD_3;
42 reg [ 1 : 0 ] Pre_MOD_3;
43
44 // Horizontal Parameter ( Pixel )
45 parameter H_SYNC_CYC = 1 ;
46 parameter H_SYNC_BACK = 151 ;
47 parameter H_SYNC_ACT = 960 ;
48 parameter H_SYNC_FRONT = 59 ;
49 parameter H_SYNC_TOTAL = 1171 ;
50
51 // Virtical Parameter ( Line )
52 parameter V_SYNC_CYC = 1 ;
53 parameter V_SYNC_BACK = 13 ;
54 parameter V_SYNC_ACT = 240 ;
55 parameter V_SYNC_FRONT = 8 ;
56 parameter V_SYNC_TOTAL = 262 ;
57
58 assign LCM_SHDB = 1 ' b1;
59 assign LCM_GRST = 1 ' b1;
60 assign LCM_DCLK = ~ iCLK;
61 assign LCM_VSYNC = mVGA_V_SYNC;
62 assign LCM_HSYNC = mVGA_H_SYNC;
63 assign LCM_DATA = (MOD_3 == 2 ' h00) ? iRed :
64 (MOD_3 == 2 ' h01) ? iGreen :
65 iBlue;
66 assign oDATA_REQ = mDATA_REQ;
67
68 always@(posedge iCLK or negedge iRST_N)
69 begin
70 if ( ! iRST_N)
71 begin
72 MOD_3 <= 2 ' b00;
73 Pre_MOD_3 <= 2 ' b00;
74 mDATA_REQ <= 1 ' b0;
75 end
76 else
77 begin
78 Pre_MOD_3 <= MOD_3;
79 if (H_Cont > H_SYNC_BACK - 2 && H_Cont < (H_SYNC_TOTAL - H_SYNC_FRONT - 2 ) &&
80 V_Cont > V_SYNC_BACK + 1 && V_Cont < (V_SYNC_TOTAL - V_SYNC_FRONT + 1 ))
81 begin
82 if (MOD_3 < 2 ' b10)
83 MOD_3 <= MOD_3 + 1 ' b1;
84 else
85 MOD_3 <= 2 ' b00;
86
87 if ((MOD_3 == 2 ' b01) && (Pre_MOD_3==2 ' b00))
88 mDATA_REQ <= 1 ' b1;
89 else
90 mDATA_REQ <= 1 ' b0;
91 end
92 else
93 begin
94 MOD_3 <= 2 ' b00;
95 mDATA_REQ <= 1 ' b0;
96 end
97 end
98 end
99
100 // H_Sync Generator, Ref. 18.42 MHz Clock
101 always@(posedge iCLK or negedge iRST_N)
102 begin
103 if ( ! iRST_N)
104 begin
105 H_Cont <= 0 ;
106 mVGA_H_SYNC <= 0 ;
107 end
108 else
109 begin
110 // H_Sync Counter
111 if (H_Cont < H_SYNC_TOTAL)
112 H_Cont <= H_Cont + 1 ;
113 else
114 H_Cont <= 0 ;
115
116 // H_Sync Generator
117 if (H_Cont < H_SYNC_CYC)
118 mVGA_H_SYNC <= 0 ;
119 else
120 mVGA_H_SYNC <= 1 ;
121 end
122 end
123
124 // V_Sync Generator, Ref. H_Sync
125 always@(posedge iCLK or negedge iRST_N)
126 begin
127 if ( ! iRST_N)
128 begin
129 V_Cont <= 0 ;
130 mVGA_V_SYNC <= 0 ;
131 end
132 else
133 begin
134 // When H_Sync Re-start
135 if (H_Cont == 0 )
136 begin
137 // V_Sync Counter
138 if (V_Cont < V_SYNC_TOTAL)
139 V_Cont <= V_Cont + 1 ;
140 else
141 V_Cont <= 0 ;
142
143 // V_Sync Generator
144 if (V_Cont < V_SYNC_CYC)
145 mVGA_V_SYNC <= 0 ;
146 else
147 mVGA_V_SYNC <= 1 ;
148 end
149 end
150 end
151
152 endmodule
完整程式碼下載
DE2_LCM_CCD.7z
Conclusion
本篇使用Verilog透過FPGA的方式控制CCD、LCM和SDRAM，實作一個簡單的數位相機，這是一個純硬體的方式，只要將FPGA燒進去之後就可以執行，下一篇 (原創) 如何在DE2將CCD影像顯示在彩色LCD上? (Nios II軟體篇 + onchip memory) (IC Design) (DE2) (Nios II) (SOPC Builder)將使用Nios II CPU，透過軟體的方式控制。
See Also
(原創) 如何在DE2將CCD影像顯示在彩色LCD上? (Nios II軟體篇 + onchip memory) (IC Design) (DE2) (Nios II) (SOPC Builder)
(原創) 如何解決DE2_LCM_CCD上下顛倒左右相反的問題? (SOC) (DE2)
(原創) 如何在DE2將CCD影像顯示在彩色LCD? (Nios II軟體篇 + μC/OS-II + SRAM + 驅動程式) (IC Design) (DE2) (Nios II) (μC/OS-II) (SOPC Builder)
(原創) 如何將CMOS彩色影像轉換成灰階影像? (SOC) (DE2)
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