FA全加器

使用的是Quatus ii 8.0 环境

首先新建工程，建立vhdl文件，编写代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity FA_xhb089 is
port( A_in_xhb089:in std_logic;
B_in_xhb089,C_in_xhb089:in std_logic;
S_out_xhb089,C_out_xhb089:out std_logic);
end FA_xhb089;

architecture one_xhb089 of FA_xhb089 is
begin
S_out_xhb089 <= A_in_xhb089 xor B_in_xhb089 xor C_in_xhb089;
C_out_xhb089 <= ( A_in_xhb089 and B_in_xhb089 ) or (( A_in_xhb089 or B_in_xhb089 ) and C_in_xhb089);
end one_xhb089;

保存，编译。

在工程中右键vhd文件生成bsf文件，即加法器的符号图。

在Processing 中点击Generate Functional Simulation Netlist,创造仿真环境

新建vwf文件，右键Insert->Insert Node or Bus->Node Finder->list all->list,把引脚添加进去，然后便是设置各种值，保存vwf文件，仿真。

新建vwf文件，

转载于:https://www.cnblogs.com/johanxu/p/5391618.html