原题:请将下面这段 C 语言描述的串行处理过程,转换为单拍完成的并行处理,并用可综合的 Verilog 来描述。
unsigned char cal_table_high_first(unsigned char value)
{
unsigned char i;
unsigned char checksum = value;
for (i=8; i>0; --i)
{
if (checksum & 0x80)
checksum = (checksum << 1) ^ 0x31;
else
checksum = (checksum << 1);
}
return checksum;
}
c语言版答案验证:#include unsigned char cal_table_high_first(unsigned char value)
{
unsigned char i;
unsigned char checksum = value; for (i=8; i>0; --i)
{ if (checksum & 0x80)
checksum = (checksum <
} return checksum;
}int main(void)
{ /* 我的第一个 C 程序 */
printf("%x",cal_table_high_first(60));
getch();
}
//输出为:b8
Verilog描述:module question_1(reset_n,clk,value,checksum);input wire reset_n,clk;input wire [7:0] value;output reg [7:0] checksum;wire[7:0] buff[8:0];always@(posedge clk,negedge reset_n) beginif(reset_n == 0) checksum <=8'b0;else checksum <= buff[0];endassign buff[8]=value;assign buff[7]=(buff[8]&8'h80)?(buff[8]<<1)^8'h31:(buff[8]<<1);assign buff[6]=(buff[7]&8'h80)?(buff[7]<<1)^8'h31:(buff[7]<<1);assign buff[5]=(buff[6]&8'h80)?(buff[6]<<1)^8'h31:(buff[6]<<1);assign buff[4]=(buff[5]&8'h80)?(buff[5]<<1)^8'h31:(buff[5]<<1);assign buff[3]=(buff[4]&8'h80)?(buff[4]<<1)^8'h31:(buff[4]<<1);assign buff[2]=(buff[3]&8'h80)?(buff[3]<<1)^8'h31:(buff[3]<<1);assign buff[1]=(buff[2]&8'h80)?(buff[2]<<1)^8'h31:(buff[2]<<1);assign buff[0]=(buff[1]&8'h80)?(buff[1]<<1)^8'h31:(buff[1]<<1);endmodule
Verilog描述的测试文件:`timescale 1ns/1nsmodule question_1_t();reg clk,reset_n;reg [7:0] value;wire [7:0] checksum;
question_1 U1 (reset_n,clk,value,checksum);always #5 clk=~clk;initial beginclk = 0;
reset_n = 0;
#20 reset_n = 1;
#10 value = 60;endendmodule
modelsim仿真:
可以看到,是在一个时钟周期完成的