卷积编码verilog实现

完成（2，1，7）编码方式 多项式为[133,171],也可以完成（2，1，5）编码方式多项式[23,35]的verilog实现

对应代码中的注释的位置。

相应的译码器也写已写完，后续。。。。。。。。。。。。。

相关的卷积编码的基础知识请参看

https://blog.csdn.net/u011639609/article/details/51476278###;

`timescale 1ns / 1ps

//
// Company:
// Engineer:
//
// Create Date: 2018/03/30 11:00:01
// Design Name:
// Module Name: ConvolutionGen_module_v2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module ConvolutionGen_module_v2(
 
 I_Clk, I_Rst,
 I_Din,I_DinEn,
 O_Dout1, O_Dout2,
 O_DoutEn

    );

input  I_Clk;
input  I_Rst;
input  I_Din;
input  I_DinEn;//输入数据

output O_Dout1;
output O_Dout2;
output O_DoutEn;

reg O_Dout1  = 'b0;
reg O_Dout2  = 'b0;
reg O_DoutEn = 'b0;

localparam   S_Idle   = 2'b01,
             S_S1_Gen = 2'b10;

reg [1:0] R_CurrentState = S_Idle;

reg R_I_Din = 'b0, R_Din = 'b0;
reg R_I_DinEn = 'b0;// R_DinEn = 'b0;
reg R_StartFlag = 'b0, R_EndFlag = 'b0;
reg R_Dout1 = 'b0, R_Dout2 = 'b0;
reg R_DoutEn = 'b0;
//reg [3:0] R_ShiftReg = 'b0;//(2.1.5)编码方式的寄存器为4bit
reg [5:0] R_ShiftReg = 'b0;//(2.1.7)

always @ ( posedge I_Clk )
begin

 if ( I_Rst )
  begin
  R_CurrentState <= S_Idle;
  end
 else
  begin
  case ( R_CurrentState )
   S_Idle:
    begin
    if ( R_StartFlag )
     begin
     R_CurrentState <= S_S1_Gen;
     end
    else
     begin
     R_CurrentState <= S_Idle;
     end
    end
   S_S1_Gen:
    begin
    if ( R_EndFlag )
     begin
     R_CurrentState <= S_Idle;
     end
    else
     begin
     R_CurrentState <= S_S1_Gen;
     end
    end
   default:
    begin
    R_CurrentState <= S_Idle;
    end
  endcase
  end
end

always @ ( posedge I_Clk )
begin
 
 R_I_Din   <= I_Din;
 R_I_DinEn <= I_DinEn;//输入数据

 R_Din   <= R_I_Din;
 //R_DinEn <= R_I_DinEn;//输入数据
 
 if ( R_CurrentState == S_Idle )
  begin
  if ( ~R_I_DinEn & I_DinEn )
   begin
   R_StartFlag <= 1'b1;
   end
  else
   begin
   R_StartFlag <= R_StartFlag;
   end
  end
 else
  begin
  R_StartFlag <= 1'b0;
  end
 
 if ( R_CurrentState == S_S1_Gen )
  begin
  if ( R_I_DinEn & ~I_DinEn )
   begin
   R_EndFlag <= 1'b1;
   end
  else
   begin
   R_EndFlag <= R_EndFlag;
   end
  end
 else
  begin
  R_EndFlag <= 1'b0;
  end
 
 if ( R_CurrentState == S_S1_Gen )
  begin
  R_Dout1 <= R_ShiftReg[5]^R_ShiftReg[4]^R_ShiftReg[2]^R_ShiftReg[1]^R_Din;
  R_Dout2 <= R_ShiftReg[5]^R_ShiftReg[2]^R_ShiftReg[1]^R_ShiftReg[0]^R_Din; //(2,1,7)
/*   R_Dout1 <= R_ShiftReg[3]^R_ShiftReg[2]^R_Din;
  R_Dout2 <= R_ShiftReg[3]^R_ShiftReg[1]^R_ShiftReg[0]^R_Din; */  //(2,1,5)
  end
 else
  begin
  R_Dout1 <= 1'b0;
  R_Dout2 <= 1'b0;
  end
 
 R_DoutEn <= R_CurrentState == S_S1_Gen;
 
 if ( R_CurrentState == S_S1_Gen )
  begin
  //R_ShiftReg <= {R_ShiftReg[2:0],R_Din};//(2,1,5)
  R_ShiftReg <= {R_ShiftReg[4:0],R_Din};//(2,1,7)
  end
 else
  begin
  R_ShiftReg <= 4'd0;
  end
 
 O_Dout1  <= R_Dout1;
 O_Dout2  <= R_Dout2;
 O_DoutEn <= R_DoutEn;
 
end
 
endmodule