左移寄存器vhdl_vhdl怎么表示8位左右移位寄存器？

这样有错吗？libraryieee;useieee.std_logic_1164.all;entityshift8isport(d,clk:instd_logic;b0,b1,b2,b3,b4,b5,b6,b7:outstd_logic);endentityshift8;architecturertlofshift8issha...

这样有错吗？

library ieee;

use ieee.std_logic_1164.all;

entity shift8 is

port(d,clk:in std_logic;

b0,b1,b2,b3,b4,b5,b6,b7:out std_logic);

end entity shift8;

architecture rtl of shift8 is

shared variable i: integer [:=0];

signal q:std_logic_vector(7 downto 0);

begin

process(clk)is

begin

if(clk'event and clk='1')then

if(d='1')then

if(i=7)then q(i)<='0';

else(q(i+1)<=q(i),

i:=i+1);

end if;

else

if(i=0)then q(i)<='0';

else(q(i-1)<=q(i),

i:=i-1);

end if;

end if;

end if;

b0<=q(0);

b1<=q(1);

b2<=q(2);

b3<=q(3);

b4<=q(4);

b5<=q(5);

b6<=q(6);

b7<=q(7);

end process;

end architecture rtl;

编译时出现了错误

ERROR:HDLParsers:164 - "D:/xilinx/shift/shift.vhd" Line 9. parse error, unexpected AFFECT, expecting RETURN or IDENTIFIER or RSQBRACK

想问一下哪里出错了

错误的位置显示在shared variable i: integer [:=0];这句

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