highp matlab,High-Level Synthesis

High-level synthesis is the process of converting a high-abstraction-level description of a design to a register-transfer-level (RTL) description for input to traditional ASIC and FPGA implementation workflows. This high-level design description can be expressed using a variety of methods, depending on the high-level synthesis tool, while the generated RTL is expressed as synthesizable Verilog® or VHDL®.

Working at a high level of abstraction lets hardware designers focus on developing the functionality in the context of a hardware architecture that meets their project requirements. Since many ASIC and FPGA designs start as algorithms in MATLAB® and Simulink®, these are natural environments to perform this design and verification.

With high-level synthesis, hardware designers can focus at a high level without implementation detail enables easy adjustment to changes, reuse across projects, and more productive functional verification.

High-level synthesis does require some amount of hardware architecture detail, such as parallelism, some notion of timing where appropriate, and hardware data types, which are usually fixed point. Most high-level synthesis users rely on graphical environments such as Simulink to visualize the architecture and data flow. Some high-level synthesis offerings such as HDL Coder™ offer automatic fixed-point conversion or even RTL implementation of native floating-point operations.

Hardware designers can also use:

HDL Coder™ to automatically generate synthesizable Verilog or VHDL code from Simulink and MATLAB for implementing hardware designs

Fixed-Point Designer™ to analyze floating-point simulations, propose fixed-point data types to accommodate the precision and ranges seen during simulation, and manage the process of applying proposed or adjusted fixed-point types

HDL Verifier™ to verify that HDL implementations from high-level synthesis —either in RTL or as netlists—are functionally correct implementations of the MATLAB code or Simulink models that describe algorithms

Simulink verification, validation, and test products to add test suite automation, formal verification, coverage, and requirements validation to high-level design and verification