离线下载器制作

基本概念预热

什么是DAP?

看下边这张图。为了访问系统资源，需要debugger传递正确的地址信息到DAP。DAP去执行这个请求。简单说就是DAP是为debugger打工的，或者说是debgger访问访问系统资源的钥匙。

 

什么是AP?

AP 不是寄存器，全名Aceess Port，也就是访问端口。AP通过使用特殊资源传递机制去访问内核中需要被调试的信息。同时，AP还可以通过AP访问机制将这些调试信息传递给DP。调试信息包括的内容：

内核的调试寄存器、ROM、memory等等。

什么是DP?

同理DP也不是寄存器，全名Debug Port(DP),也就是调试端口。DP提供接口访问AP中的信息。DP根据不同的物理连接方式可以分为：JTAG-DP、SW-DP、SWJ-DP。

硬件准备&连接

模拟SWD接口的板子简称为Host,目标MCU(即我要连接的板子)简称为Target。

Host                                                      Target

swdio      -------------------------------->      swdio

swclk      -------------------------------->      swclk

GND    --------------------------------->       GND   

Host板上的swdio swclk用普通gpio模拟。直接用杜邦线连接到目标板上已经创建好的SWD接口（注意：目标板上的SWD接口，不需要再重定义，板子上一般都带有SWD接口）以我的板子为例，奉上一副原理图：

                                                                                                                      

这里自己迈过一个坑：将目标板上的SWDIO 和 SWCLK引脚也用普通GPIO引脚进行模拟,出现的问题是始终得不到理想的预期。如果能得到回复才怪。

这里还有一个问题：需不需要连接目标板的RESET引脚。在看网络上的一些开源代码的时候，有复位目标板的内容。这里自己做了个实验不需要RESET引脚连接也是可以的。自己可以下看下离线下载器的确也是不需要RESET引脚的，下图为离线下载器的引脚图定义：

                                                                                                                                                           

现在硬件连接完毕，当然别忘了给两个板子供电，这里就不在赘述到硬件连接上。

 

SW-DP 协议&时序

SWD:串行调试总线接口

SWD协议的理解主要是参看官方文档《debug_interface_v5_2_architecture_specification_IHI0031E》，以下也是摘自官方文档，同时附上自己的理解。

The Arm SWD interface uses a single bidirectional data connection and a separate clock to transfer data

synchronously. An operation on the wire consists of two or three phases:

 

Packet request

The external host debugger issues a request to the DP. The DP is the target of the request.

Acknowledge response

The target sends an acknowledge response to the host.

Data transfer phase

This phase is only present when either:

• A data read or data write request is followed by a valid (OK) acknowledge response.

• The CTRL/STAT.ORUNDETECT flag is 0b1.

The data transfer is one of:

• Target to host, following a read request (RDATA).

• Host to target, following a write request (WDATA).

 上边的大概意思是：Arm SWD接口使用单个双向数据连接和单独的时钟来同步传输数据。一个操作在总线上大概包含两三步操作：因为是同步传输信息，因此需要SWCLK同步时钟。

1、数据访问请求：外部主机debugger请求访问目标机的DP

2、ACK响应。目标机回复ACK给主机

3、数据传输：读写

When the SW-DP receives a packet request from the debug host, it must respond immediately by entering the

acknowledge phase. There is a turnaround period between these phases, as they are in different directions. If a data

phase is required, it follows immediately after the acknowledge phase.

 

当SW-DP接收到来自主机的请求时，它应该立即回复ACK，在这些阶段中应该有个turnaround周期（在代码视线中没有体现，也可）。如果一个读数据被请求，那么这个数据应该在回复ACK响应之后，立即回复。

 

For a write request, there is a turnaround period between the acknowledge phase and the WDATA data transfer

phase. Following the WDATA data transfer phase the host continues to drive the wire. There is no additional

turnaround period.

 

对于写数据请求，有一个turnaround周期在ACK阶段和数据传输阶段。在数据传输后，主机继续驱动总线，没有额为的turnaround周期

 

For a read request, there is no turnaround period between the acknowledge phase and the data transfer phase. There

is a turnaround period following the RDATA data transfer phase, following which the host drives the wire.

 

对于读数据请求，没有turnaround周期在ACK和数据传输阶段。有一个turnaround在读取数据传输阶段。

 

To ensure that the transfer can be clocked through the SW-DP, after the data transfer phase the host must do one of

the following:

• Immediately start a new SWD operation with the start bit of a new packet request.

• Continue to drive the SWD interface with idle cycles until the host starts a new SWD operation.

• If the host is driving the SWD clock, continue to clock the SWD interface with at least eight idle cycles. After

completing this sequence, the host can stop the clock.

 

为了确保传输能够通过SW-DP时钟进行，在数据传输后，主机必须做以下的事情之一：

 

1：立刻开启一个新的SWD操作通过一个新的数据包请求起始位。

 

2：继续驱动SWD接口通过空闲周期直至主机开始了一个新的SWD操作。也就是说可以不做SWD的新操作。

 

3：如果主机正在驱动SWD时钟，请继续以至少八个空闲周期为SWD接口提供时钟。 完成此序列后，主机可以停止时钟。

 

SWD protocol versions

 

SWD protocol version 1 is a point-to-point architecture, supporting connection between a single host and a single

device. It permits connection to multiple devices by providing extra connections from the host, which has several

disadvantages:

 

• It complicates the physical connection standard, by having variants with different numbers of connections.

 

• It increases the number of pins that are required for the connector on the device PCB, which is unacceptable

where size is a limiting factor.

 

• It increases the number of pins that are required on a package with multiple dies inside.

 

• It makes it difficult to integrate multiple platforms that are accessed by the SWD protocol into the same chip.

Techniques to solve this require connections that are shared between multiple Serial Wire devices. These

connections are detrimental to the maximum speed of operation, but in many situations they provide an acceptable

trade-off.

 

SWD protocol version 2 is a multi-drop architecture that:

 

• Enables a two-wire host connection to communicate simultaneously with multiple devices.

 

• Permits an effectively unlimited number of devices to be connected simultaneously, subject to electrical

constraints.

 

• Is largely backwards-compatible, because provision for multi-drop support in a device does not break

point-to-point compatibility with existing host equipment that does not support the multi-drop extensions.

For more information, see SWD protocol versions.

 

• Permits a device to power down completely, while the device is not selected.

 

• Prevents multiple devices from driving the wire simultaneously, and continues to support the wire being

actively driven both HIGH and LOW, maintaining a high maximum clock speed.

 

• Permits multi-drop connections incorporating devices that do not implement the SWD protocol.

 

SWD协议版本1是点对点体系结构，支持单个主机和单个设备之间的连接。 通过提供来自主机的额外连接，它允许连接到多个设备，这有几个缺点：

1、通过具有具有不同数量的连接的变量，它使物理连接标准变得复杂。

等等。。。不再解释。目前用不到这种一对多的架构。

Line turnaround

To prevent contention, a turnaround period is required when the device driving the wire changes. For the turnaround

period, neither the host nor the target drives the wire, and the state of the wire is undefined. See also Line pull-up

on page B4-123.

 

为了防止争用，当驱动电线的设备发生变化时，需要一个周转期。 在周转期间，主机和目标都不会驱动电线，并且电线的状态不确定。

 

Note

The line turnaround period can provide for pad delays when using a high sample clock frequency.

The length of the turnaround period is controlled by DLCR.TURNROUND. The default setting is a turnaround

period of one clock cycle.

 

Idle cycles

 

After completing a transaction, the host must either insert idle cycles or continue immediately with the start bit of

a new transaction.

The host clocks the SWD interface with the line LOW to insert idle cycles.

 

完成事务后，主机必须插入空闲周期或立即以新事务的起始位继续。

 

B4.1.5 Bit order

 

All data values in SWD operations are transferred LSB first.

 

LSB传输，不再赘述下边有栗子介绍

 

For example, the OK response of 0b001 appears on the wire as 1, followed by 0, followed by 0, as shown in

Figure B4-1 on page B4-112 and Figure B4-2 on page B4-112.

 

B4.1.6 Parity

 

A simple parity check is applied to all packet request and data transfer phases. Even parity is used:

 

简单的奇偶校验将应用于所有数据包请求和数据传输阶段。

 

Packet requests

• If the number of bits with a value of 0b1 is odd, the parity bit is set to 0b1.

• If the number of bits with a value of 0b1 is even, the parity bit is set to 0b0.

 

Data transfers (WDATA and RDATA)

The parity check is made over the 32 data bits WDATA[0:31] or RDATA[0:31]:

• If the number of bits with a value of 0b1 is odd, the parity bit is set to 0b1.

• If the number of bits with a value of 0b1 is even, the parity bit is set to 0b0.

The packet request parity bit is shown in each of the diagrams in this section, from Figure B4-1 on page B4-112 to

Figure B4-7 on page B4-116. It appears on the wire immediately after the A[2:3] bits. A parity error in the packet

request is detected by the SW-DP, which responds with a protocol error. See Protocol error response on

page B4-114.

The WDATA parity bit is shown in Figure B4-1 on page B4-112 and in Figure B4-7 on page B4-116. It appears on

the wire immediately after the WDATA[31] bit. A parity error in the WDATA data transfer phase is detected by the

SW-DP and, other than writes to TARGETSEL, recorded in CTRL/STAT.WDATAERR. If overrun detection is

enabled, it is IMPLEMENTATION DEFINED whether CTRL/STAT.STICKYORUN is set to 0b1. A parity error in a write

to TARGETSEL deselects the target.

If a SWD write parity error occurs, the transaction is discarded and the register is not updated. This applies to both

DP and AP writes.

The RDATA parity bit is shown in Figure B4-2 on page B4-112. It appears on the wire immediately after the

RDATA[31] bit. The debugger must check for parity errors in the RDATA data transfer phase and retry the read if

necessary.

Note

The ACK[0:2] bits are never included in the parity calculation. Debuggers must remember this principle when

parity checking the data from a read operation, when the debugger receives a continuous stream of 36 bits, as shown

in Figure B4-2 on page B4-112:

• Bits 0-2 are ACK[0:2].

• Bits 3-34 are RDATA[0:31].

• Bit 35 is the parity bit.

The parity check must be applied to bits 3-34 of this block of data, and the result must be compared with bit 35, the

parity bit.

 

重点

 

SWD protocol operation 

 

The illustrations of the different possible operations use the following terms:

 

Start

 

A single start bit, with value 0b1.

 

起始位始终为0x01。

 

 

APnDP

A single bit, indicating whether the Debug Port or the Access Port Access register is to be accessed.

This bit is 0b0 for a DPACC access, or 0b1 for an APACC access.

 

该为为0表示访问的是DPACC寄存器。该位为1表示访问的是APACC寄存器

 

RnW

A single bit, indicating whether the access is a read or a write. This bit is 0b0 for a write access, or

0b1 for a read access.

 

该位为0表示将要进行写操作。该位为1表示将要进行读操作。

 

A[2:3]

Two bits, giving the A[3:2] address field for the DP or AP register Address:

• For a DPACC access, the register being addressed depends on the A[3:2] value and, if

A[3:2]==0b01, the value that is held in SELECT. DPBANKSEL. For details, see:

—

DP architecture version 1 (DPv1) address map on page B2-50

—

DP architecture version 2 (DPv2) address map on page B2-51.

• For an APACC access, the register being addressed depends on the A[3:2] value and the value

that is held in SELECT.{APSEL,APBANKSEL}. For details about addressing, see:

—

MEM-AP Programmers’ Model on page C2-168 for accesses to a MEM-AP register

—

JTAG-AP register summary on page C3-202 for accesses to a JTAG-AP register.

 

两位数据内容为：DP或者AP寄存器的地址。

 

Note

The A[3:2] value is transmitted Least Significant Bit (LSB) first on the wire, which is why it appears

as A[2:3] on the diagrams.

Parity

A single parity bit for the preceding packet. See Parity on page B4-108.

 

Stop

A single stop bit. In the synchronous SWD protocol, this bit is always 0b0.

Park

A single bit. The host must drive the Park bit HIGH to park the line before tristating it for the

turnaround period, to ensure that the line is read as HIGH by the target, which is required because

the pull-up on the SWD interface is weak. The target reads this bit as 0b1.

Trn

Turnaround. See Line turnaround on page B4-107

 

 

读命令为 数据头+Trn+ACK+RDATA+Parity构成，但实际操作发现Trn这位是忽略掉的（所以不知道对此Trn的理解是否有误），即发送完数据头后立即读入ACK，判断Target是否正确响应。

写命令为数据头+Trn+ACK+Trn+WDATA+Parity，在这不同的是，在写命令时必须要考虑2个Trn的位置

 SWD协议传输前操作：

首先我们需要读取目标板IDCODE，具体操作实现为：

先进行一次LineReset,LineReset具体实现为：先保证Host连续送出至少50个“1”，使得Target进行Line Reset。随后发送0xE79E(LSB)接着再一次LineReset，随后便可以读IDCODE。F1系列读取的是0x1BA01477。

读取完ID_CODE寄存器，需要去连接到AHB-AP了。用DP寄存器的SELECT来进行选择。然后读取下APID 。实际读出来是0x14770011（F103）

上述操作完成后，说明连接是建立了，可以进行下一步程序下载操作。

源码

  时序的实现。

上边巴拉巴拉介绍了一堆东西，那么需要怎样用程序实现协议，并通过调试解决，这个开发过程中出现的问题，才是成长的过程。只有这样在以后如果遇到没有任何开源代码可以分享学习，只有份协议可供参考的情况下，才不至于懵逼。

未完待续。。