SWD protocol versions
SWD protocol version 1 is a point-to-point architecture, supporting connection between a single host and a single
device. It permits connection to multiple devices by providing extra connections from the host, which has several
disadvantages:
• It complicates the physical connection standard, by having variants with different numbers of connections.
• It increases the number of pins that are required for the connector on the device PCB, which is unacceptable
where size is a limiting factor.
• It increases the number of pins that are required on a package with multiple dies inside.
• It makes it difficult to integrate multiple platforms that are accessed by the SWD protocol into the same chip.
Techniques to solve this require connections that are shared between multiple Serial Wire devices. These
connections are detrimental to the maximum speed of operation, but in many situations they provide an acceptable
trade-off.
SWD protocol version 2 is a multi-drop architecture that:
• Enables a two-wire host connection to communicate simultaneously with multiple devices.
• Permits an effectively unlimited number of devices to be connected simultaneously, subject to electrical
constraints.
• Is largely backwards-compatible, because provision for multi-drop support in a device does not break
point-to-point compatibility with existing host equipment that does not support the multi-drop extensions.
For more information, see SWD protocol versions.
• Permits a device to power down completely, while the device is not selected.
• Prevents multiple devices from driving the wire simultaneously, and continues to support the wire being
actively driven both HIGH and LOW, maintaining a high maximum clock speed.
• Permits multi-drop connections incorporating devices that do not implement the SWD protocol.
SWD协议版本1是点对点体系结构,支持单个主机和单个设备之间的连接。 通过提供来自主机的额外连接,它允许连接到多个设备,这有几个缺点:
Idle cycles
After completing a transaction, the host must either insert idle cycles or continue immediately with the start bit of
a new transaction.
The host clocks the SWD interface with the line LOW to insert idle cycles.
完成事务后,主机必须插入空闲周期或立即以新事务的起始位继续。
B4.1.5 Bit order
All data values in SWD operations are transferred LSB first.
LSB传输,不再赘述下边有栗子介绍
For example, the OK response of 0b001 appears on the wire as 1, followed by 0, followed by 0, as shown in
Figure B4-1 on page B4-112 and Figure B4-2 on page B4-112.
B4.1.6 Parity
A simple parity check is applied to all packet request and data transfer phases. Even parity is used:
简单的奇偶校验将应用于所有数据包请求和数据传输阶段。
Packet requests
• If the number of bits with a value of 0b1 is odd, the parity bit is set to 0b1.
• If the number of bits with a value of 0b1 is even, the parity bit is set to 0b0.
Data transfers (WDATA and RDATA)
The parity check is made over the 32 data bits WDATA[0:31] or RDATA[0:31]:
• If the number of bits with a value of 0b1 is odd, the parity bit is set to 0b1.
• If the number of bits with a value of 0b1 is even, the parity bit is set to 0b0.
The packet request parity bit is shown in each of the diagrams in this section, from Figure B4-1 on page B4-112 to
Figure B4-7 on page B4-116. It appears on the wire immediately after the A[2:3] bits. A parity error in the packet
request is detected by the SW-DP, which responds with a protocol error. See Protocol error response on
page B4-114.
The WDATA parity bit is shown in Figure B4-1 on page B4-112 and in Figure B4-7 on page B4-116. It appears on
the wire immediately after the WDATA[31] bit. A parity error in the WDATA data transfer phase is detected by the
SW-DP and, other than writes to TARGETSEL, recorded in CTRL/STAT.WDATAERR. If overrun detection is
enabled, it is IMPLEMENTATION DEFINED whether CTRL/STAT.STICKYORUN is set to 0b1. A parity error in a write
to TARGETSEL deselects the target.
If a SWD write parity error occurs, the transaction is discarded and the register is not updated. This applies to both
DP and AP writes.
The RDATA parity bit is shown in Figure B4-2 on page B4-112. It appears on the wire immediately after the
RDATA[31] bit. The debugger must check for parity errors in the RDATA data transfer phase and retry the read if
necessary.
Note
The ACK[0:2] bits are never included in the parity calculation. Debuggers must remember this principle when
parity checking the data from a read operation, when the debugger receives a continuous stream of 36 bits, as shown
in Figure B4-2 on page B4-112:
• Bits 0-2 are ACK[0:2].
• Bits 3-34 are RDATA[0:31].
• Bit 35 is the parity bit.
The parity check must be applied to bits 3-34 of this block of data, and the result must be compared with bit 35, the
parity bit.
重点
SWD protocol operation
The illustrations of the different possible operations use the following terms:
Start
A single start bit, with value 0b1.
起始位始终为0x01。
APnDP
A single bit, indicating whether the Debug Port or the Access Port Access register is to be accessed.
This bit is 0b0 for a DPACC access, or 0b1 for an APACC access.
该为为0表示访问的是DPACC寄存器。该位为1表示访问的是APACC寄存器
RnW
A single bit, indicating whether the access is a read or a write. This bit is 0b0 for a write access, or
0b1 for a read access.
该位为0表示将要进行写操作。该位为1表示将要进行读操作。
A[2:3]
Two bits, giving the A[3:2] address field for the DP or AP register Address:
• For a DPACC access, the register being addressed depends on the A[3:2] value and, if
A[3:2]==0b01, the value that is held in SELECT. DPBANKSEL. For details, see:
—
DP architecture version 1 (DPv1) address map on page B2-50
—
DP architecture version 2 (DPv2) address map on page B2-51.
• For an APACC access, the register being addressed depends on the A[3:2] value and the value
that is held in SELECT.{APSEL,APBANKSEL}. For details about addressing, see:
—
MEM-AP Programmers’ Model on page C2-168 for accesses to a MEM-AP register
—
JTAG-AP register summary on page C3-202 for accesses to a JTAG-AP register.
两位数据内容为:DP或者AP寄存器的地址。
Note
The A[3:2] value is transmitted Least Significant Bit (LSB) first on the wire, which is why it appears
as A[2:3] on the diagrams.
Parity
A single parity bit for the preceding packet. See Parity on page B4-108.
Stop
A single stop bit. In the synchronous SWD protocol, this bit is always 0b0.
Park
A single bit. The host must drive the Park bit HIGH to park the line before tristating it for the
turnaround period, to ensure that the line is read as HIGH by the target, which is required because
the pull-up on the SWD interface is weak. The target reads this bit as 0b1.
Trn
Turnaround. See Line turnaround on page B4-107
读命令为 数据头+Trn+ACK+RDATA+Parity构成,但实际操作发现Trn这位是忽略掉的(所以不知道对此Trn的理解是否有误),即发送完数据头后立即读入ACK,判断Target是否正确响应。
写命令为数据头+Trn+ACK+Trn+WDATA+Parity,在这不同的是,在写命令时必须要考虑2个Trn的位置
SWD协议传输前操作:
首先我们需要读取目标板IDCODE,具体操作实现为:
先进行一次LineReset,LineReset具体实现为:先保证Host连续送出至少50个“1”,使得Target进行Line Reset。随后发送0xE79E(LSB)接着再一次LineReset,随后便可以读IDCODE。F1系列读取的是0x1BA01477。
读取完ID_CODE寄存器,需要去连接到AHB-AP了。用DP寄存器的SELECT来进行选择。然后读取下APID 。实际读出来是0x14770011(F103)
上述操作完成后,说明连接是建立了,可以进行下一步程序下载操作。