verilog 乘法_如何用Verilog设计一个复数乘法器

复数乘法原理

 a = a_i + j * a_q
 b = b_i + j * b_q
 ​
   (a_i + j * a_q) * (b_i + j * b_q)
 = a_i * b_i + j * a_q * b_i + j * a_i * b_q - a_q * b_q
 = (a_i * b_i - a_q * b_q) + j * (a_i * b_q + a_q * b_i)
 ​
 result_i = a_i * b_i - a_q * b_q
 result_q = a_i * b_q + a_q * b_i

如上式子化简，需要四个乘法器。先算出乘法再算出加法。

该式子还可以进一步化简

 result_i = a_i * b_i - a_q * b_q
          = a_i * b_i - a_q * b_q+ a_i * b_q - a_i * b_q
          = a_i * (b_i + b_q) - b_q * (a_i + a_q)
          
 result_q = a_i * b_q + a_q * b_i
          = a_i * b_q + a_q * b_i + a_i * b_i - a_i * b_i
          = a_i * (b_i + b_q) - b_i * (a_i - a_q)
 ​
 result_i = a_i * (b_i + b_q) - b_q * (a_i + a_q) 
 result_q = a_i * (b_i + b_q) - b_i * (a_i - a_q)<