verilog线程

线程：

module test;
  reg [7:0]y=15;

  initial begin
    y=255;
  end

  always@(*)begin
        $display("1%0t, %b", $realtime, y);
  end
endmodule

module test1;
  reg y1=1;

  initial begin
     y1=0;
  end
endmodule

编译之后：
一共5个线程，第一个是给y初值，第二个是test的initial，第三个是test的always，第四个是test1的赋初值，第五个是test1的initial

S_0x5636787e1a30 .scope module, "test" "test" 2 2;
S_0x5636788186b0 .scope module, "test1" "test1" 2 14;

    .scope S_0x5636787e1a30;
T_0 ;                            //test1的变量初始化线程
    %pushi/vec4 15, 0, 8;
    %store/vec4 v0x563678818860_0, 0, 8;
    %end;
    .thread T_0;

    .scope S_0x5636787e1a30;
T_1 ;                            //test1的initial线程
    %pushi/vec4 255, 0, 8;
    %store/vec4 v0x563678818860_0, 0, 8;
    %end;
    .thread T_1;

    .scope S_0x5636787e1a30;
T_2 ;                            //test1的always线程
    %wait E_0x563678818cb0;
    %vpi_call 2 10 "$display", "1%0t, %b", $realtime, v0x563678818860_0 {0 0 0};
    %jmp T_2;
    .thread T_2, $push;

    .scope S_0x5636788186b0;
T_3 ;                            //test2的变量初始化线程       
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x5636788276d0_0, 0, 1;
    %end;
    .thread T_3;

    .scope S_0x5636788186b0;
T_4 ;                            //test2的initial线程   
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x5636788276d0_0, 0, 1;
    %end;
    .thread T_4;