![v2-eb058f10034b07805dc0eada57025ef8_1440w.jpg?source=172ae18b](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-eb058f10034b07805dc0eada57025ef8_1440w.jpg?source=172ae18b)
一、Baugh-Wooley算法
Baugh-Wooley算法是由Baugh和Wooley于1973年提出的二进制补码并行阵列相乘算法。该算法转化为等效并行阵列相加,其中每个部分和为乘数和被乘数比特相与,并且所有的部分和符号位为“+”。将n比特X,Y,乘法结果2n比特的P表示如下:
![v2-a061f2d4fe771cc007c7a0bfc793ebb8_b.jpg](http://img-01.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-a061f2d4fe771cc007c7a0bfc793ebb8_b.jpg)
![v2-4291062322428f42dc1b11974d7d630f_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic4.zhimg.com/v2-4291062322428f42dc1b11974d7d630f_b.jpg)
从上式看出,XY相乘,结果P=XY相当于前两项减去后两项正数,设为A和B.
按顺序用字母表示以上项,即P = C+D-(A+B)。
将最后两项A和B,补0扩展表示成2n位,以便在阵列中相加:
![v2-bec844bc43fa89ded64833fc8abc0745_b.png](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-bec844bc43fa89ded64833fc8abc0745_b.png)
其中ai=y(n-1)*xi
A的二进制表示如下:
![v2-877f27aa25bcec4137666437cf10f30b_b.png](http://img-01.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic4.zhimg.com/v2-877f27aa25bcec4137666437cf10f30b_b.png)
-A,即A的二进制补码,对A“取反加一”,表示如下:
取反:
![v2-40e7d4be8f07809ad93887d696e08123_b.png](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic4.zhimg.com/v2-40e7d4be8f07809ad93887d696e08123_b.png)
加一:
![v2-467b8565762316817e85651a389759ea_b.png](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic3.zhimg.com/v2-467b8565762316817e85651a389759ea_b.png)
B的补码表示与A同理。
所以,-(A+B)的结果如下,即-A-B:
![v2-76ab9777ed4edb45bad8dec60b6c391f_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic4.zhimg.com/v2-76ab9777ed4edb45bad8dec60b6c391f_b.jpg)
将-A-B代入P的表达式,所以P的结果如下:
![v2-f696339a8d7f5071207fdc29c240c785_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-f696339a8d7f5071207fdc29c240c785_b.jpg)
以n=4比特X,Y相乘为例,P=XY为8比特:
![v2-6c5179cd27c0ddfdd9a57c1edb51ac74_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-6c5179cd27c0ddfdd9a57c1edb51ac74_b.jpg)
该4*4 乘法器结构如下:
![v2-f429d38cc4c78a8d0788598eb206f9e8_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-f429d38cc4c78a8d0788598eb206f9e8_b.jpg)
以上结果中每个框均为全加器,有微小差距。
蓝色框,其中某个输入为xiyi相与;
绿色框,其中某个输入为xiyi相与后取反;
右下斜对角为P的传播路径,上下为进位传播路径,最长的进位传播链为P0的进位至P7的进位传播。
![v2-caddab86f6da754fc6a831d0863001f0_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-caddab86f6da754fc6a831d0863001f0_b.jpg)
二、Verilog设计
设计一个16比特或者32比特的Baugh-Wooley乘法器,位宽N可自定义,默认为16比特。
几个要点:
(1)蓝色框与绿色框全加器;
(2)橙色框模块,最后一级加法器,作为示例,此处采用RCA加法器;
(3)xiyi, ci, si, co, so信号生成;
(4)Baugh-Wooley结构连接;
(5)乘法结果输出P选择。
根据以上结构拓展成16比特的结构如下:
![v2-657a3be7adb30e03774ebaade952bfc1_b.jpg](http://img-01.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-657a3be7adb30e03774ebaade952bfc1_b.jpg)
在Verilog中,可罗列出每个模块,并连接。为了便于参数化,根据如上结构划分为5部分,每一部分使用generate…endgenerate生成。
![v2-69dc8c2af7c3534a8a086377038d930b_b.jpg](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic4.zhimg.com/v2-69dc8c2af7c3534a8a086377038d930b_b.jpg)
![v2-b78ac941902f7e7a34d8b33ef45594e1_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-b78ac941902f7e7a34d8b33ef45594e1_b.jpg)
![v2-6aaf579c7c247d822f047883b66e9136_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic3.zhimg.com/v2-6aaf579c7c247d822f047883b66e9136_b.jpg)
![v2-02ebe6cea6c3c49da34c9274ee8b787c_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-02ebe6cea6c3c49da34c9274ee8b787c_b.jpg)
![v2-7dc595692195be0ec39c941956eef628_b.jpg](http://img-02.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic1.zhimg.com/v2-7dc595692195be0ec39c941956eef628_b.jpg)
![v2-c0a008372eb8399c3abedb3d74bbe6c9_b.jpg](http://img-03.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic2.zhimg.com/v2-c0a008372eb8399c3abedb3d74bbe6c9_b.jpg)
Baugh-Wooley乘法器,Verilog源码公众号回复“00e”。
参考资料:
《A Two's Complement Parallel Array Multiplication Algorithm》
《Baugh-Wooley Multiplier》
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![v2-5f62185ff9e8ffa46f3fb9ea3eb90cba_b.jpg](http://img-01.proxy.5ce.com/view/image?&type=2&guid=d8cf06af-f02f-eb11-8da9-e4434bdf6706&url=https://pic3.zhimg.com/v2-5f62185ff9e8ffa46f3fb9ea3eb90cba_b.jpg)