彩灯控制器课程设计vhdl_vhdl语言设计一个8路彩灯控制器

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2014-03-05 回答

library ieee;

use ieee.std_logic_1164.all;

entity fengxi is port(

q:in std_logic_vector(5 downto 0);

rst,adjust,clk:in std_logic;

y:out std_logic_vector(7 downto 0));

end;

architecture behavioal of fengxi is

type states is (s0,s1,s2,s3,s4,s5,s6);

signal state:states;

signal k:integer range 0 to 3;

signal en,clk_low,clk_use:std_logic;

signal y_out,y_out1:std_logic_vector(7 downto 0);

begin

process(clk,rst)--分频

begin

if rst='1' then

k<=0;clk_low<='0';

else

if(clk'event and clk='1') then

if k=3 then

k<=0; clk_low<=not clk_low;

else

k<=k+1;

end if;

end if;

end if;

end process;

proce