AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories16 Kbytes +16 Kbytes of I-cache and D-cacheUp to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-W...
AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
16 Kbytes +16 Kbytes of I-cache and D-cache
Up to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-Write capability
A high-speed master direct memory access (MDMA) controller, two dual-port DMAs with FIFO and request router capabilities for optimal peripheral management, and one additional DMA
Chrom-ART acceleration for efficient 2D image copy and double-precision FPU are also part of the acceleration features available in the device
Peripheral speed independent from CPU speed (dual-clock support) allowing system clock changes without any impact on peripheral operations
Even more peripherals, such as four serial audio inteRFaces (SAI) with SPDIF output support, three full-duplex I²S interfaces, a SPDIF input interface supporting four inputs, two USB OTG with dedicated power supply and Dual-mode
最低0.47元/天 解锁文章
2309
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
