8分频verilog线_七、八分频电路Verilog源代码

八分频

模块文件：

module

div8(clk_i,clk_o,reset);

parameter

DIV_N = 8;

input

clk_i;

input

reset;

output

clk_o;

reg

clk_o;

integer

count;

always @

(negedge reset or posedge clk_i)

begin

if(!reset)

count

<= 0;

else

if(count

== 7)

count

<= 0;

else

count

<= count + 1;

end

always @

(negedge reset or posedge clk_i)

begin

if(!reset)

clk_o <= 0;

else

begin

if(count <= (DIV_N/2 - 1))

clk_o <= 0;

else

clk_o <= 1;

end

end

endmodule

测试文件：

`include

"div8.v"