计数器 buaa Verilog 练习1 计组

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    15:30:43 10/07/2021 
// Design Name: 
// Module Name:    code 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module code(
    input Clk,
    input Reset,
    input Slt,
    input En,
    output reg [63:0] Output0,
    output reg [63:0] Output1
    );

    //integer count1 = 0; // q1
	 reg [1:0] count1 = 2'b01; //assign 1, not 0


    // sequential logic
    always @(posedge Clk) begin
        if (Reset == 1'b1) begin
            Output0 <= 64'h0000_0000; // match the identifier's bit width
            Output1 <= 64'h0000_0000;
				count1 <= 2'b01; // reset will also reset the valid time Periodd
            //count1 <= 0; // why not
        end 
        else if (En == 1'b1) begin
            if (Slt == 1'b0) begin
                Output0 <= Output0 + 64'h0000_0001; // match the bit width
                Output1 <= Output1;            
            end
            else begin
                count1 <= count1 + 2'b01;
                if (count1 == 2'b00) begin
                    Output0 <= Output0;
                    Output1 <= Output1 + 64'h0000_0001;
                end
                else begin
                    Output0 <= Output0;
                    Output1 <= Output1;
                end
            end
        end
        else begin
            Output0 <= Output0;
            Output1 <= Output1;
        end
    end


endmodule