2021-01-26

ADS8866  3-Wire CS Mode
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this
interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 43). As
shown in Figure 44, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the
state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to
select other devices on the board. However, CONVST must return high before the minimum conversion time
(t conv-min ) elapses and is held high until the maximum possible conversion time (t conv-max ) elapses.

 

 

When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning
as CS) can be brought low after the maximum conversion time (t conv-max ) elapses. On the CONVST falling edge,
DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on
subsequent SCLK falling edges. Data can be read at either SCLK falling or rising edges. Note that with any
SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the
t h_CK_DO-min time frame. DOUT goes to 3-state after the 16th SCLK falling edge or when CONVST goes high,
whichever occurs first.