NE5532运放加法器

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分类专栏：硬件电路设计文章标签：模拟加法器运放

于 2019-08-25 11:22:39 首次发布

本文链接：https://blog.csdn.net/weixin_42107954/article/details/100061236

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原理图

PCB

规格书

模拟加法器就是把两个信号混到一起。

这里用的是NE5532运放做的一个加法器

原理图

PCB

经过测试，是能够正常使用的。

规格书

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the timedelay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a lowimpedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5-V supply, output levels are compatible with TTL inputs.

这些设备是精密定时电路，能够
产生精确的时间延迟或振荡。在延时或单稳态操作模式下，定时间隔为
由单个外部电阻器和电容器网络控制。
在不稳定运行模式下，频率和占空比
循环可以通过两个外部独立控制
电阻器和单个外部电容器。
阈值和触发水平通常为三分之二和
分别占VCC的三分之一。这些级别可以更改
通过使用控制电压端子。当触发输入
低于触发电平，触发器被设置，输出
走高。如果触发输入高于触发水平，并且
阈值输入高于阈值水平，触发器
复位，输出低。重置（reset）输入可以
覆盖所有其他输入，可用于启动新的
定时周期。当RESET变低时触发器复位，
并且输出变低。当输出低时，在放电（DISCH）和
地面。
输出电路能够吸收或向上提供电流
至200mA。操作规定适用于5V至15V的电源。
使用5V电源，输出电平与TTL兼容
输入。

Monostable Operation For monostable operation, any of the ‘555 timers can be connected as shown in Figure 1. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the internal flip-flop and drives the output high. Capacitor C is then charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the internal flip-flop, drives the output low, and discharges C.

单稳态运行
对于单稳态操作，可以如图1所示连接任何555定时器。如果输出低，则应用
触发器的负向脉冲（TRIG）设置内部触发器并驱动输出为高。然后对电容器C进行充电
通过RA，直到电容器两端的电压达到阈值（THRES）输入的阈值电压。如果TRIG有
回到高电平后，阈值比较器的输出重置内部触发器，将输出驱动为低电平，以及
放电C。

Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 10μs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10μs, which limits the minimum monostable pulse width to 10μs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tW = 1.1RAC. Figure 3 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.

当TRIG电压降至触发阈值以下时，启动单稳态操作。一旦启动，序列只会结束
如果TRIG在定时间隔结束前至少10μs处于高电平。当触发器接地时，比较器存储器
时间可以长达10μs，这将最小单稳态脉冲宽度限制在10μs。由于阈值水平和
Q1的饱和电压，输出脉冲持续时间约为tW=1.1RAC。图3是
RA和C的各种值。阈值水平和充电率都与电源电压VCC成正比。
因此，只要电源电压在该时间段内保持恒定，定时间隔就与电源电压无关
间隔。
在定时间隔期间同时向RESET和TRIG施加负向触发脉冲，放电C和
从复位脉冲的正沿开始重新启动循环。只要复位脉冲为
低。为防止误触发，当不使用RESET时，应将其连接到VCC。