Armv9.4 体系结构扩展--原文版

已于 2024-08-21 15:43:49 修改
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于 2024-08-19 21:15:18 首次发布
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👉👉👉 ARMv8/ARMv9架构入门到精通-[目录] 👈👈👈

The Armv9.4 architecture extension

The Armv9.4 architecture extension is an extension to Armv9.3. It adds mandatory and optional architectural features. Some features must be implemented together. An implementation is Armv9.4 compliant if all of the following apply:

  • It is Armv8.9 compliant.

  • It is Armv9.3 compliant.

  • It includes all of the Armv9.4 architectural features that are mandatory.

An Armv9.4 compliant implementation can additionally include:

  • Armv9.4 features that are optional.

FEAT_ABLE, Address Breakpoint Linking Extension

FEAT_ABLE introduces the capability to link a watchpoint to an address matching breakpoint.

This feature is supported in both AArch64 and AArch32 states.

FEAT_ABLE is OPTIONAL from Armv9.3.

If FEAT_ABLE is implemented, then FEAT_BWE is implemented.

If FEAT_ABLE is implemented, then FEAT_Debugv8p9 is implemented.

The following fields identify the presence of FEAT_ABLE:

  • ID_AA64DFR1_EL1.ABLE.

  • EDDFR1.ABLE.

For more information, see ‘About Breakpoint exceptions’.

FEAT_BWE, Breakpoint and watchpoint enhancements

FEAT_BWE introduces the capability to define an included-range-based breakpoint and an excluded-range-based breakpoint.

This feature is supported in AArch64 state only.

FEAT_BWE is OPTIONAL from Armv9.3.

The following fields identify the presence of FEAT_BWE:

  • ID_AA64DFR1_EL1.ABLE.

  • EDDFR1.ABLE.

  • ID_AA64DFR2_EL1.BWE.

  • EDDFR2.BWE.

For more information, see ‘Other usage constraints for Address breakpoints’.

FEAT_CHK, Check Feature Status

FEAT_CHK introduces the CHKFEAT instruction, which allows software to detect when certain features are enabled.

A PE that is compliant with architectures from Armv8.0 to Armv9.3 is compliant with the behavior defined for this feature.

This feature is supported in AArch64 state only.

FEAT_CHK is OPTIONAL from Armv8.0.

FEAT_CHK is mandatory from Armv9.4.

For more information, see ‘Detecting when FEAT_GCS is enabled’.

FEAT_D128, 128-bit Translation Tables, 56 bit PA

FEAT_D128 introduces support for the VMSAv9-128 translation system, comprising the following:

  • 128-bit translation table descriptors.

  • 56-bit physical addresses.

  • 56-bit virtual addresses.

  • 128-bit System registers.

  • 128-bit atomic instructions.

  • TLBIP VA, TLBIP RVA, TLBIP IPA, TLBIP RIPA instructions that can take 128-bit inputs.

  • IMPLEMENTATION DEFINED System instructions that can take 128-bit inputs.

This feature is supported in AArch64 state only.

FEAT_D128 is OPTIONAL from Armv9.3.

If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented.

If FEAT_D128 is implemented, then FEAT_SYSINSTR128 is implemented.

If FEAT_D128 is implemented, then FEAT_LSE128 is implemented.

If FEAT_D128 is implemented, then FEAT_S1PIE is implemented.

If FEAT_D128 is implemented, then FEAT_S2PIE is implemented.

If FEAT_D128 is implemented, then FEAT_AIE is implemented.

If FEAT_D128 is implemented, then FEAT_TCR2 is implemented.

If FEAT_D128 is implemented, then FEAT_LVA is implemented.

If FEAT_D128 is implemented, then FEAT_LPA2 is implemented.

The following field identifies the presence of FEAT_D128:

  • ID_AA64MMFR3_EL1.D128.

For more information, see ‘The AArch64 Virtual Memory System Architecture’.

FEAT_EBEP, Exception-based Event Profiling

FEAT_EBEP provides support for reporting PMU counter overflows as PMU Profiling exceptions. This allows generation of higher quality profiles by eliminating the interrupt latency and jitter incurred outside the PE.

This feature is supported in both AArch64 and AArch32 states.

FEAT_EBEP is OPTIONAL from Armv9.3.

In an Armv9.3 implementation, if FEAT_PMUv3p9 is implemented, FEAT_EBEP is implemented.

When FEAT_EBEP and FEAT_AA64EL2 are implemented, FEAT_FGT2 is implemented.

When FEAT_EBEP and FEAT_AA32EL0 are implemented, FEAT_Debugv8p9 is implemented.

The following field identifies the presence of FEAT_EBEP:

  • ID_AA64DFR1_EL1.EBEP.

For more information, see ‘Exception-based event profiling’.

FEAT_ETEv1p3, Embedded Trace Extension version 1.3

FEAT_ETEv1p3 extends FEAT_ETE to support all of the following:

  • The ETE External Debug Request, when FEAT_Debugv8p9 is implemented.

  • The ETE Trace Output Enable, which is mandatory for FEAT_ETEv1p3 and OPTIONAL for FEAT_ETE.

This feature is supported in AArch64 state, and performs trace in both AArch64 and AArch32 states.

FEAT_ETEv1p3 is OPTIONAL from Armv9.3.

If FEAT_ETEv1p3 is implemented, then FEAT_ETEv1p2 is implemented.

The following field identifies the presence of FEAT_ETEv1p3:

  • TRCDEVARCH.REVISION.

For more information, see ‘The Embedded Trace Extension’.

FEAT_GCS, Guarded Control Stack Extension

FEAT_GCS introduces support for a Guarded Control Stack, an area of memory in which procedure return addresses and exception return addresses are stored and protected from modification.

This feature is supported in AArch64 state only.

FEAT_GCS is OPTIONAL from Armv9.3.

If FEAT_GCS is implemented, then FEAT_CHK is implemented.

If FEAT_GCS is implemented, then FEAT_S1PIE is implemented.

The following field identifies the presence of FEAT_GCS:

  • ID_AA64PFR1_EL1.GCS.

For more information, see ‘Guarded Control Stack’.

FEAT_ITE, Instrumentation Trace Extension

FEAT_ITE provides all of the following to allow software to inject instrumentation information into the ETE trace stream:

  • The TRCIT instruction, that injects the value of a general purpose register into the ETE trace stream.

  • ‘Instrumentation Packet’ that contains the value written by the TRCIT instruction.

  • Controls that define the behavior of the TRCIT instruction.

This feature is supported in both AArch64 and AArch32 states.

FEAT_ITE is OPTIONAL from Armv9.3.

If FEAT_ITE is implemented, then FEAT_TRF is implemented.

If FEAT_ITE is implemented, then FEAT_ETE is implemented.

If FEAT_ITE is implemented, then FEAT_TRBE is implemented.

When FEAT_ITE and FEAT_AA64EL2 are implemented, FEAT_FGT2 is implemented.

The following fields identify the presence of FEAT_ITE:

  • ID_AA64DFR1_EL1.ITE.

  • TRCIDR0.ITE.

For more information, see:

  • ‘Instrumentation extension’.

  • ‘Instrumentation element’.

FEAT_LSE128, 128-bit Atomics

FEAT_LSE128 introduces support for 128-bit atomic instructions.

This feature is supported in AArch64 state only.

FEAT_LSE128 is OPTIONAL from Armv9.3.

If FEAT_LSE128 is implemented, then FEAT_LSE is implemented.

The following field identifies the presence of FEAT_LSE128:

  • ID_AA64ISAR0_EL1.Atomic.

For more information, see:

  • ‘Atomic memory operations’.

  • ‘Swap’.

FEAT_LVA3, 56-bit VA

FEAT_LVA3 introduces support for 56-bit virtual addresses.

This feature is supported in AArch64 state only.

FEAT_LVA3 is OPTIONAL from Armv9.3.

If FEAT_LVA3 is implemented, then FEAT_D128 is implemented.

If FEAT_LVA3 is implemented, then FEAT_LVA is implemented.

The following field identifies the presence of FEAT_LVA3:

  • ID_AA64MMFR2_EL1.VARange.

For more information, see ‘Supported virtual address ranges’.

FEAT_SEBEP, Synchronous Exception-based Event Profiling

FEAT_SEBEP creates configurations to generate synchronous and precise PMU Profiling exceptions.

This feature is supported in both AArch64 and AArch32 states.

FEAT_SEBEP is OPTIONAL from Armv9.3.

If FEAT_SEBEP is implemented, then FEAT_EBEP is implemented.

When FEAT_SEBEP and FEAT_AA64EL2 are implemented, FEAT_FGT2 is implemented.

When FEAT_SEBEP and FEAT_AA32EL0 are implemented, FEAT_Debugv8p9 is implemented.

The following field identifies the presence of FEAT_SEBEP:

  • ID_AA64DFR0_EL1.SEBEP.

For more information, see:

  • ‘Synchronous exception-based event profiling’.

  • ‘Synchronous events’.

FEAT_SME2p1, Scalable Matrix Extension version 2.1

The Scalable Matrix Extension version 2.1 (SME2.1) is a superset of SME2 that adds:

  • Additional SME instructions.

  • Other relaxations and enhancements.

In this Manual, unless stated otherwise, when SME is used, the behavior also applies to SME2.1.

This feature is supported in AArch64 state only.

FEAT_SME2p1 is OPTIONAL from Armv9.2.

In an Armv9.4 implementation, if FEAT_SME2 is implemented, FEAT_SME2p1 is implemented.

If FEAT_SME2p1 is implemented, then FEAT_SME2 is implemented.

If FEAT_SME and FEAT_SVE2p1 are implemented, then FEAT_SME2p1 is implemented.

The following field identifies the presence of FEAT_SME2p1:

  • ID_AA64SMFR0_EL1.SMEver.

For more information, see:

  • ‘Data processing - SME, SME2’.

  • ‘The Scalable Matrix Extension’.

FEAT_SME_B16B16, Non-widening BFloat16 to BFloat16 SME ZA-targeting arithmetic.

FEAT_SME_B16B16 introduces SME ZA-targeting non-widening BFloat16 floating-point instructions to SME.

This feature is supported in AArch64 state only.

FEAT_SME_B16B16 is OPTIONAL from Armv9.2.

If FEAT_SME_B16B16 is implemented, then FEAT_SME2 is implemented.

If FEAT_SME_B16B16 is implemented, then FEAT_SVE_B16B16 is implemented.

The following field identifies the presence of FEAT_SME_B16B16:

  • ID_AA64SMFR0_EL1.B16B16.

FEAT_SME_F16F16, Non-widening half-precision FP16 to FP16 arithmetic for SME2.

FEAT_SME_F16F16 introduces the SME2 half-precision to single-precision convert instructions and non-widening half-precision floating-point instructions.

This feature is supported in AArch64 state only.

FEAT_SME_F16F16 is OPTIONAL from Armv9.2.

If FEAT_SME_F16F16 is implemented, then FEAT_SME2 is implemented.

The following field identifies the presence of FEAT_SME_F16F16:

  • ID_AA64SMFR0_EL1.F16F16.

For more information, see:

  • ‘Data processing - SME, SME2’.

  • ‘The Scalable Matrix Extension’.

FEAT_SVE2p1, Scalable Vector Extensions version 2.1

The Scalable Vector Extension version 2.1 (SVE2.1) is a superset of SVE2 that adds:

  • SVE instructions in Non-streaming SVE mode, which were previously added by SME in Streaming SVE mode. These are:

    • Contiguous multi-vector load and store instructions.

    • Predicate-as-counter instructions.

    • General-purpose SVE instructions.

  • Other relaxations and enhancements.

In this Manual, unless stated otherwise, when SVE is used, the behavior also applies to SVE2.1.

This feature is supported in AArch64 state only.

FEAT_SVE2p1 is OPTIONAL from Armv9.2.

In an Armv9.4 implementation, if FEAT_SVE2 is implemented, FEAT_SVE2p1 is implemented.

If FEAT_SVE2p1 is implemented, then FEAT_SVE2 is implemented.

If FEAT_SVE2 and FEAT_SME2p1 are implemented, then FEAT_SVE2p1 is implemented.

The following field identifies the presence of FEAT_SVE2p1:

  • ID_AA64ZFR0_EL1.SVEver.

For more information, see:

  • FEAT_SVE.

  • ‘Loads and stores - SME, SME2, SVE2p1’.

  • ‘Data processing - SVE2’.

FEAT_SVE_B16B16, Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2.

FEAT_SVE_B16B16 introduces the following:

  • Advanced SIMD: Non-widening BFloat16 floating-point instructions to SVE, and multi-vector Z-targeting non-widening BFloat16 floating-point instructions to SME.

  • SVE: SVE non-widening BFloat16 instructions when the PE is not in Streaming SVE mode.

  • SME: The SVE non-widening BFloat16 instructions when the PE is in Streaming SVE mode.

  • SME: The SME Z-targeting multi-vector non-widening BFloat16 instructions.

This feature is supported in AArch64 state only.

FEAT_SVE_B16B16 is OPTIONAL from Armv9.2.

If FEAT_SVE_B16B16 is implemented, then FEAT_SME2 or FEAT_SVE2 is implemented.

The following field identifies the presence of FEAT_SVE_B16B16:

  • ID_AA64ZFR0_EL1.B16B16.

For more informations, see:

  • ‘BFloat16 arithmetic’.

  • ‘BFloat16 minimum/maximum’.

  • ‘Clamp to minimum/maximum’.

FEAT_SYSINSTR128, 128-bit System instructions

FEAT_SYSINSTR128 introduces support for IMPLEMENTATION DEFINED System instructions that can take 128-bit inputs.

This feature is supported in AArch64 state only.

FEAT_SYSINSTR128 is OPTIONAL from Armv9.3.

If FEAT_SYSINSTR128 is implemented, then FEAT_SCTLR2 is implemented.

If FEAT_SYSINSTR128 is implemented, then FEAT_D128 is implemented.

The following field identifies the presence of FEAT_SYSINSTR128:

  • ID_AA64ISAR2_EL1.SYSINSTR_128.

For more information, see ‘System instructions’.

FEAT_SYSREG128, 128-bit System registers

FEAT_SYSREG128 introduces the following support for 128-bit System registers:

  • The MRRS instruction to move a 128-bit System register into a pair of 64-bit general-purpose registers.

  • The MSRR instruction to move a pair of 64-bit general-purpose registers to a 128-bit System register.

  • 128-bit formats of the following system registers:

  • The Physical Address Register, PAR_EL1.

  • The Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.

  • The following translation table base address registers, TTBR0_EL1, TTBR0_EL2, TTBR1_EL1, TTBR1_EL2, VTTBR_EL2.

This feature is supported in AArch64 state only.

FEAT_SYSREG128 is OPTIONAL from Armv9.3.

If FEAT_SYSREG128 is implemented, then FEAT_SCTLR2 is implemented.

If FEAT_SYSREG128 is implemented, then FEAT_D128 is implemented.

The following field identifies the presence of FEAT_SYSREG128:

  • ID_AA64ISAR2_EL1.SYSREG_128.

FEAT_TRBE_EXT, Trace Buffer external mode

FEAT_TRBE_EXT allows an external debugger, as well as a self-hosted debugger, to use the Trace Buffer Unit. All of the following registers are introduced to determine the parameters of the implementation:

  • TRBDEVARCH.

  • TRBDEVID.

  • TRBDEVID1.

This feature is supported in both AArch64 and AArch32 states.

FEAT_TRBE_EXT is OPTIONAL from Armv9.3.

If FEAT_TRBE_EXT is implemented, then FEAT_TRBE is implemented.

The following fields identify the presence of FEAT_TRBE_EXT:

  • ID_AA64DFR0_EL1.ExtTrcBuff.

  • EDDFR.TraceBuffer.

  • EDDFR.ExtTrcBuff.

For more information, see Trace buffer External mode.

FEAT_TRBE_MPAM, Trace Buffer MPAM extensions

FEAT_TRBE_MPAM allows software to program the MPAM PARTID and PMG to use different MPAM values for trace data. TRBDEVID1.{PMG_MAX, PARTID_MAX} are used to determine the parameters of the MPAM implementation.

This feature is supported in both AArch64 and AArch32 states.

FEAT_TRBE_MPAM is OPTIONAL from Armv9.3.

If FEAT_TRBE_MPAM is implemented, then FEAT_TRBE_EXT is implemented.

If FEAT_TRBE_MPAM is implemented, then FEAT_MPAM is implemented.

When FEAT_TRBE_MPAM and FEAT_AA64EL2 are implemented, FEAT_FGT2 is implemented.

The following field identifies the presence of FEAT_TRBE_MPAM:

  • TRBIDR_EL1.MPAM.

For more information, see ‘External mode and FEAT_MPAM’.

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