采用流水线操作,可以提高运算速度,但8位乘8位消耗了128和逻辑单元。
需要注意:
- SLL逻辑左移(SRL右移),最左边的数会被移出,最右边补0,只能对BIT类型使用;SLA算数左移(SRA右移),最左边的数会被移出,最右边补1;ROL循环左移(ROR右移),最左边的数会被循环移到右边。
- BIT类型不能执行‘+’操作。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY mult IS
PORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY;
ARCHITECTURE behave OF mult IS
SIGNAL sum_a: BIT_VECTOR(7 DOWNTO 0);
SIGNAL sum_b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL sum_0: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_2: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_3: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_4: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_5: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_6: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_7: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_01: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_23: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_45: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_67: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_02: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum_46: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
sum_a <= TO_BITVECTOR(a);
sum_b <= TO_BITVECTOR(b);
sum_0 <= TO_STDLOGICVECTOR("00000000" & sum_b) WHEN sum_a(0) = '1' ELSE
"0000000000000000";
sum_1 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 1) WHEN sum_a(1) = '1' ELSE
"0000000000000000";
sum_2 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 2) WHEN sum_a(2) = '1' ELSE
"0000000000000000";
sum_3 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 3) WHEN sum_a(3) = '1' ELSE
"0000000000000000";
sum_4 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 4) WHEN sum_a(4) = '1' ELSE
"0000000000000000";
sum_5 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 5) WHEN sum_a(5) = '1' ELSE
"0000000000000000";
sum_6 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 6) WHEN sum_a(6) = '1' ELSE
"0000000000000000";
sum_7 <= TO_STDLOGICVECTOR(("00000000" & sum_b) SLL 7) WHEN sum_a(7) = '1' ELSE
"0000000000000000";
sum_01 <= sum_0+sum_1;
sum_23 <= sum_2+sum_3;
sum_45 <= sum_4+sum_5;
sum_67 <= sum_6+sum_7;
sum_02 <= sum_01+sum_23;
sum_46 <= sum_45+sum_67;
c <= sum_02+sum_46;
END ARCHITECTURE behave;
运算过程如下: