FLASH(M25P16)-READ指令时序代码及仿真波形（内含M25P16仿真模型文件）

最新推荐文章于 2023-08-22 17:50:41 发布

ICer_Wx

最新推荐文章于 2023-08-22 17:50:41 发布

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分类专栏： FPGA协议

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READ

本文代码实现读取仿真模型文件初始化文本中第一个地址的数据，可以看到仿真模型中初始化文件是initM25P16.txt，

将其一个地址数据改为12

READ时序图

READ指令代码

module flash_read (
	input		wire		clk,
	input		wire		rst_n,
	
	output	reg		flash_cs_n,
	output	reg		flash_scl,
	output	reg		flash_d,
	
	input		wire		flash_q,
	
	output	reg		q
);

	localparam		READ		=	8'h03;
	localparam		T_half	=	5;
	localparam 		ADDR		=  24'h000000;
	
	always @ (posedge clk) q <= flash_q;
	
	reg	[8:0]		cnt;
	
	always @ (posedge clk) begin
		if (rst_n == 0)
			cnt <= 0;
		else if (cnt == 406)
					cnt <= cnt;
			  else
					cnt <= cnt + 1'b1;
	end 
	
	always @ (*) begin
		if (rst_n == 0) begin flash_cs_n = 1; flash_d = 0; flash_scl = 0; end
		else	case (cnt)
						0					    :	 begin flash_cs_n = 1; flash_d = 0; flash_scl = 0; end
						1					    :  begin flash_cs_n = 0; flash_d = READ[7];end
						1 + T_half * 1	    :	 begin flash_scl = 1;end
						1 + T_half * 2     :  begin flash_scl = 0; flash_d = READ[6];end
						1 + T_half * 3	    :	 begin flash_scl = 1;end
						1 + T_half * 4     :  begin flash_scl = 0; flash_d = READ[5];end
						1 + T_half * 5	    :	 begin flash_scl = 1;end
						1 + T_half * 6     :  begin flash_scl = 0; flash_d = READ[4];end
						1 + T_half * 7	    :	 begin flash_scl = 1;end
						1 + T_half * 8     :  begin flash_scl = 0; flash_d = READ[3];end
						1 + T_half * 9	    :	 begin flash_scl = 1;end
						1 + T_half * 10    :  begin flash_scl = 0; flash_d = READ[2];end
						1 + T_half * 11 	 :	 begin flash_scl = 1;end
						1 + T_half * 12    :  begin flash_scl = 0; flash_d = READ[1];end
						1 + T_half * 13 	 :	 begin flash_scl = 1;end
						1 + T_half * 14    :  begin flash_scl = 0; flash_d = READ[0];end
						1 + T_half * 15 	 :	 begin flash_scl = 1;end
						1 + T_half * 16    :  begin flash_scl = 0;flash_d = ADDR[23];end
						1 + T_half * 17    :  begin flash_scl = 1;end 
						1 + T_half * 18    :  begin flash_scl = 0;flash_d = ADDR[23]; end
						1 + T_half * 19    :  begin flash_scl = 1; end
						1 + T_half * 20    :  begin flash_scl = 0;flash_d = ADDR[22]; end
						1 + T_half * 21    :  begin flash_scl = 1; end
						1 + T_half * 22    :  begin flash_scl = 0;flash_d = ADDR[21]; end
						1 + T_half * 23    :  begin flash_scl = 1; end
						1 + T_half * 24    :  begin flash_scl = 0;flash_d = ADDR[20]; end
						1 + T_half * 25    :  begin flash_scl = 1; end
						1 + T_half * 26    :  begin flash_scl = 0;flash_d = ADDR[19]; end
						1 + T_half * 27    :  begin flash_scl = 1; end
						1 + T_half * 28    :  begin flash_scl = 0;flash_d = ADDR[18]; end
						1 + T_half * 29    :  begin flash_scl = 1; end
						1 + T_half * 30    :  begin flash_scl = 0;flash_d = ADDR[17]; end
						1 + T_half * 31    :  begin flash_scl = 1; end
						1 + T_half * 32    :  begin flash_scl = 0;flash_d = ADDR[16]; end
						1 + T_half * 33    :  begin flash_scl = 1; end
						1 + T_half * 34    :  begin flash_scl = 0;flash_d = ADDR[15]; end
						1 + T_half * 35    :  begin flash_scl = 1; end
						1 + T_half * 36    :  begin flash_scl = 0;flash_d = ADDR[14]; end
						1 + T_half * 37    :  begin flash_scl = 1; end
						1 + T_half * 38    :  begin flash_scl = 0;flash_d = ADDR[13]; end
						1 + T_half * 39    :  begin flash_scl = 1; end
						1 + T_half * 40    :  begin flash_scl = 0;flash_d = ADDR[12]; end
						1 + T_half * 41    :  begin flash_scl = 1;end 
						1 + T_half * 42    :  begin flash_scl = 0;flash_d = ADDR[11]; end
						1 + T_half * 43    :  begin flash_scl = 1; end
						1 + T_half * 44    :  begin flash_scl = 0;flash_d = ADDR[10]; end
						1 + T_half * 45    :  begin flash_scl = 1; end
						1 + T_half * 46    :  begin flash_scl = 0;flash_d = ADDR[9]; end
						1 + T_half * 47    :  begin flash_scl = 1; end
						1 + T_half * 48    :  begin flash_scl = 0;flash_d = ADDR[8]; end
						1 + T_half * 49    :  begin flash_scl = 1; end
						1 + T_half * 50    :  begin flash_scl = 0;flash_d = ADDR[7]; end
						1 + T_half * 51    :  begin flash_scl = 1; end
						1 + T_half * 52    :  begin flash_scl = 0;flash_d = ADDR[6]; end
						1 + T_half * 53    :  begin flash_scl = 1; end
						1 + T_half * 54    :  begin flash_scl = 0;flash_d = ADDR[5]; end
						1 + T_half * 55    :  begin flash_scl = 1; end
						1 + T_half * 56    :  begin flash_scl = 0;flash_d = ADDR[4]; end
						1 + T_half * 57    :  begin flash_scl = 1; end
						1 + T_half * 58    :  begin flash_scl = 0;flash_d = ADDR[3]; end
						1 + T_half * 59    :  begin flash_scl = 1; end
						1 + T_half * 60    :  begin flash_scl = 0;flash_d = ADDR[2]; end
						1 + T_half * 61    :  begin flash_scl = 1; end
						1 + T_half * 62    :  begin flash_scl = 0;flash_d = ADDR[1]; end
						1 + T_half * 63    :  begin flash_scl = 1;end
						1 + T_half * 64    :  begin flash_scl = 0;flash_d = ADDR[0]; end
						1 + T_half * 65    :  begin flash_scl = 1;end
						1 + T_half * 66    :  begin flash_scl = 0;end
						1 + T_half * 67    :  begin flash_scl = 1;end
						1 + T_half * 68    :  begin flash_scl = 0;end
						1 + T_half * 69    :  begin flash_scl = 1;end
						1 + T_half * 70    :  begin flash_scl = 0;end
						1 + T_half * 71    :  begin flash_scl = 1;end
						1 + T_half * 72    :  begin flash_scl = 0;end
						1 + T_half * 73    :  begin flash_scl = 1;end
						1 + T_half * 74    :  begin flash_scl = 0;end
						1 + T_half * 75    :  begin flash_scl = 1;end
						1 + T_half * 76    :  begin flash_scl = 0;end
						1 + T_half * 77    :  begin flash_scl = 1;end
						1 + T_half * 78    :  begin flash_scl = 0;end
						1 + T_half * 79    :  begin flash_scl = 1;end
						1 + T_half * 80    :  begin flash_scl = 0;end
						1 + T_half * 81    :  begin flash_scl = 1;end
						default			    :	 ;		
				endcase
	end 
endmodule

READ仿真代码

`timescale 1ns/1ps
module flash_read_tb;

reg		clk;
reg		rst_n;

wire		flash_cs_n;
wire		flash_d;
wire		flash_scl;

wire		flash_q;

wire		q;

	flash_read flash_read_inst(
										.clk				(clk),
										.rst_n			(rst_n),
										
										.flash_cs_n		(flash_cs_n),
										.flash_scl		(flash_scl),
										.flash_d			(flash_d),
										
										.flash_q			(flash_q),
										
										.q					(q)
);

	m25p16 m25p16_inst(
										.c					(flash_scl),
										.data_in			(flash_d),
										.s					(flash_cs_n),
										.w					(1'b1),
										.hold				(1'b1),
										.data_out		(flash_q)
);

initial clk = 1;
always #10 clk = ~clk;

initial begin
	rst_n = 0;
	#201
	rst_n = 1;
	repeat (500)
		@ (posedge clk);
	#200
	$stop;
end 
endmodule

仿真结果