Abridged Data Sheet
DS28E01-100
1K-Bit Protected 1-Wire EEPROM with
SHA-1 Engine
GENERAL DESCRIPTION FEATURES
The DS28E01-100 combines 1024 bits of EEPROM 1024 bits of EEPROM memory partitioned into
with challenge-and-response authentication security four pages of 256 bits
implemented with the ISO/IEC 10118-3 Secure Hash On-chip 512-bit SHA-1 engine to compute 160-bit
Algorithm (SHA-1). The 1024-bit EEPROM array is Message Authentication Codes (MAC) and to
configured as four pages of 256 bits with a 64-bit generate secrets
scratchpad to perform write operations. All memory Write access requires knowledge of the secret
pages can be write protected, and one page can be and the capability of computing and transmitting
put in EPROM-emulation mode, where bits can only a 160-bit MAC as authorization
be changed from a 1 to a 0 state. Each DS28