Verilog在vivodo中实现真双口RAM IP Core读写操作

功能代码：

`timescale 1ns / 1ps
module ram_16(
    input clk,
    input rst_n	 
);
	reg ena;//总使能控制
	reg wren1;//RAM1使能
	reg wren2;//RAM2使能
	reg [7:0] addr;//8位地址位
	reg [7:0] writedata;//写入数据
	reg [7:0] readdata;//读取数据
	wire [7:0] readdata_flag;
	
	reg state;//状态寄存器


always @ (posedge clk or negedge rst_n)//写地址信号控制0~15
begin
    if(!rst_n) 
		begin
		ena <= 0;
		wren1 <= 0;
		wren2 <= 0;
		addr <= 0;
		writedata <= 0;
		state <= 0;
		end
    else 
	begin
	case(state)
	0:begin
        if(addr < 255)//RAM1中0~255地址写数据
		begin 
			addr <= addr + 1;
			ena <= 1;
			wren1 <= 1;
		end
		else
		begin
			addr <= 0; //转到下一个状态，地址清0，开始读
			state <= 1;
			wren1 <= 0;
			wren2 <= 1;
		end
		if(writedata < 255)
			writedata <= writedata + 1;
		else 
			writedata <= 0;
			
	1:begin
		if(addr < 255)
		begin
			addr <= addr + 1;
			wren2 <= 1;
			wren1 <= 0;
			readdata_flag = readdata;
		end
		else 
		begin
			state <= 0;
			addr <= 0;
		end
	end
	dafault:state <= state;
	endcase
	
	end
end	

blk_mem_gen_0 u1 (
  .clka(clk),      //写端口
  .ena(ena),    
  .wea(wren1),      
  .addra(addr),  
  .dina(writedata),   
  .douta(), 
  
  .clkb(clk),      //读端口
  .enb(ena),      
  .web(wren2),      
  .addrb(addr),  
  .dinb(8'd0),    
  .doutb(readdata) 
);
endmodule				

testbench：

`timescale 1ns / 1ps
module TB();
reg clk;
reg rst_n;

always #5 clk = ~clk;
endmodule