用verilog写一个流水灯

下面是一个简单的Verilog代码，实现了流水灯效果：

module traffic_light (input clk, output reg red, yellow, green);
   parameter delay = 5;
   reg [31:0] counter = 0;
   always @ (posedge clk) begin
      if (counter == delay) begin
         counter <= 0;
         red <= ~red;
         yellow <= ~yellow;
         gre