verilog流水灯-CSDN博客

本文链接：https://blog.csdn.net/liuli66635/article/details/139041245

//top.v

`timescale 1ns / 1ps

//sw0-restn;sw1-enable
//sw3-12hz;sw567-led
module top(
input wire clk_100m, // 时钟信号
input wire rstn, // 复位信号
input wire enable, // 使能信号
input wire sw_12,
input wire [2:0] sw_led,
output wire [7:0] led, // 8个LED灯输出
output wire [7:0] digit,// 数码管第一位
output wire [1:0] dis_sel
// output reg [7:0] digit2 // 数码管第二位
);
wire [7:0] digit1; // 数码管第一位
wire [7:0] digit2; // 数码管第二位
wire clk_temp;
wire clk_temp1;
wire clk_1ms;

clk_wiz_0 u1
(
// Clock out ports
.clk_out1(clk_temp), // output clk_out1
// Clock in ports
.clk_in1(clk_100m)); // input clk_in1
clk12 u2 (
.clk_10M(clk_temp), // input wire clk_10M
.resetn(rstn), // input wire resetn
.sw_12(sw_12), // input wire sw_12
.clk1(clk_temp1) , // output wire clk1
.clk_dis(clk_1ms)
);
style u3(
.clk1(clk_temp1),
.rstn(rstn),
.enable(enable),
.sw_led(sw_led),
.led(led)
);
seg_de u4(
.ti_num(sw_12),
.sel_num(sw_led),
.rstn(rstn),
.seg_ti(digit1),
.seg_one(digit2)
);
seg_sel u5(
.clk_dis(clk_1ms),
.seg_ti(digit1),
.seg_one(digit2),
.digit(digit),
.selone(dis_sel)

);

endmodule

//style.v 控制流水灯样式

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/15 19:03:31
// Design Name:
// Module Name: style
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

module style(
input clk1,
input rstn,
input enable,
input [2:0] sw_led,
output reg [7:0] led
);

reg [2:0] count = 0;

always @(posedge clk1 or negedge rstn) begin
if (!rstn) begin
count <= 0;
led <= 8'b00000000;
end else begin
case(sw_led)
// 模式1: 单个LED依次点亮
3'b001: begin
if (count == 3'd0) begin
led <= 8'b10000000;
end
else if (enable==0) led<=led;
else if (count != 3'd3) //begin
led <= {led[6:0], led[7]};
count <= count + 1;

// end else if (count == 4'd2) begin
// led <= 8'b00000100;
// end else if (count == 4'd3) begin
// led <= 8'b00001000;
// end
end

// 模式2: 交替点亮相邻的两个LED
3'b010: begin
if (count == 3'd3) begin
led <= 8'b00000011;
count<=0;
end
else if (enable==0) led<=led;
else begin
led <= {led[1:0], led[7:2]};
count <= count + 1;

end
end

// 模式3: 两个LED同时点亮，向两端移动
3'b011: begin
if (count == 3'b011) begin
led <= 8'b00000011;
count<=0;
end
else if (enable==0) led<=led;
else begin
led <= {led[5:0], led[7:6]};
count <= count + 1;

end
end

// 模式4: 循环左移
3'b100: begin
if (count ==3'd0) begin
led <= 8'b10000000;
end
else if (enable==0) led<=led;
else //begin
led <= {led[0], led[7:1]};
count <= count + 1;

end

default: led <= 8'b00000000;
endcase


end
end

endmodule

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/15 19:55:09
// Design Name:
// Module Name: seg_sel
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

//数码管片选模块
module seg_sel(
input clk_dis,
input [7:0] seg_ti, seg_one,
output reg [7:0] digit,
output reg [1:0] selone
);
initial selone=2'b01;
always @ (posedge clk_dis) begin
selone={selone[0],selone[1]};
end
always @ (posedge clk_dis) begin
case(selone)
2'b01:digit <=seg_ti;
2'b10:digit <=seg_one;
default:digit <=8'b10000000;
endcase
end
endmodule

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/15 19:54:44
// Design Name:
// Module Name: seg_de
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

//数码管译码模块
module seg_de(
input ti_num,
input [2:0] sel_num,
input rstn,
output reg [7:0] seg_ti, seg_one
);
//wire one,ten;
//assign one = ti_num % 10; //个位
//assign ten = ti_num / 10 % 10; //十位

// always @ ( * ) begin
// case( ten )
// 0: begin seg_ten = 8'b1100_0000; end // g -> a
// 1: begin seg_ten = 8'b1111_1001; end
// 2: begin seg_ten = 8'b1010_0100; end
// 3: begin seg_ten = 8'b1011_0000; end
// 4: begin seg_ten = 8'b1001_1001; end
// 5: begin seg_ten = 8'b1001_0010; end
// 6: begin seg_ten = 8'b1000_0010; end
// 7: begin seg_ten = 8'b1111_1000; end
// 8: begin seg_ten = 8'b1000_0000; end
// 9: begin seg_ten = 8'b1001_0000; end
// default: begin seg_ten = 8'b1100_0000; end
// endcase
// end

   always @ ( * ) begin
   if(rstn==0) seg_ti = 8'b00111111;
   else
case( ti_num+1'b1 )
// 2'b00: begin seg_ti = 8'b1100_0000; end // g -> a
2'b01: begin seg_ti = 8'b00000110; end
2'b10: begin seg_ti = 8'b01011011; end
// 3: begin seg_ti = 8'b1011_0000; end
// 4: begin seg_ti = 8'b1001_1001; end
// 5: begin seg_ti = 8'b1001_0010; end
// 6: begin seg_ti = 8'b1000_0010; end
// 7: begin seg_ti = 8'b1111_1000; end
// 8: begin seg_ti = 8'b1000_0000; end
// 9: begin seg_ti = 8'b1001_0000; end
default: begin seg_ti = 8'b00111111; end
endcase
end

   always @ ( * ) begin
   if(rstn==0) seg_one = 8'b00111111;
   else
case( sel_num )
// 0: begin seg_sel = 8'b00111111; end // g -> a
1: begin seg_one = 8'b00000110; end
2: begin seg_one = 8'b01011011; end
3: begin seg_one = 8'b01001111; end
4: begin seg_one = 8'b01100110; end
// 5: begin seg_sel = 8'b1001_0010; end
// 6: begin seg_sel = 8'b1000_0010; end
// 7: begin seg_sel = 8'b1111_1000; end
// 8: begin seg_sel = 8'b1000_0000; end
// 9: begin seg_sel = 8'b1001_0000; end
default: begin seg_one = 8'b00111111; end
endcase
end
endmodule

//产生1hz、2hz时钟

//可以生成ip核后添加

module clk12(
input wire clk_10M,
input resetn,
input sw_12,
output reg clk1,
output reg clk_dis
);
reg [30:0] t;
reg [30:0] cnt;
reg [5:0] num;
initial clk1 = 1'b0;

always@(posedge clk_10M or negedge resetn)begin
case(sw_12)
1'b1:begin
if(resetn == 1'b0)
cnt <= 30'b0;
else if(cnt == 2499999)//要2hz就2499999
begin
cnt <= 30'b0;
clk1 <= ~clk1;
end
else
cnt <= cnt + 1'b1;
end
1'b0:begin
if(resetn == 1'b0)
cnt <= 30'b0;
else if(cnt == 4999999)//要1hz就4999999
begin
cnt <= 30'b0;
clk1 <= ~clk1;
end
else
cnt <= cnt + 1'b1;
end

endcase

end

reg [13:0]cnt1;

always@(posedge clk_10M or negedge resetn)
if(resetn == 1'b0)
begin
clk_dis <=1'b0;
cnt1 <= 8'b0;
end
// else if(cnt == 499)
else if(cnt1 == 4999)
begin
cnt1 <= 14'b0;
clk_dis <= ~clk_dis;
end
else
cnt1 <= cnt1 + 1'b1;
endmodule

//测试模块

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/15 22:38:31
// Design Name:
// Module Name: led_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

module led_tb();
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/15 19:02:05
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

reg clk_100m; // 时钟信号
reg rstn; // 复位信号
reg enable; // 使能信号
reg sw_12;
reg [2:0] sw_led;
wire[7:0] led; // 8个LED灯输出
wire[7:0] digit;// 数码管第一位
wire[1:0] dis_sel;
// output reg [7:0] digit2 // 数码管第二位

wire [7:0] digit1; // 数码管第一位
wire [7:0] digit2; // 数码管第二位
wire clk_temp;
wire clk_temp1;
wire clk_1ms;
always #5 clk_100m<= ~clk_100m;
initial
begin
clk_100m=0;
rstn=0;
enable=1;
sw_12=1;
#50 rstn<=1;
#100000 sw_led<=3'b001;
#100000 sw_led<=3'b011;
#100000 sw_led<=3'b010;
#100000 sw_led<=3'b100;
#100 rstn<=0;
#5000 rstn<=1;
#20000sw_12<=0;
end
clk_wiz_0 u1
(
// Clock out ports
.clk_out1(clk_temp), // output clk_out1
// Clock in ports
.clk_in1(clk_100m)); // input clk_in1
clk12_0 u2 (
.clk_10M(clk_temp), // input wire clk_10M
.resetn(rstn), // input wire resetn
.sw_12(sw_12), // input wire sw_12
.clk1(clk_temp1) , // output wire clk1
.clk_dis(clk_1ms)
);
style u3(
.clk1(clk_temp1),
.rstn(rstn),
.enable(enable),
.sw_led(sw_led),
.led(led)
);
seg_de u4(
.ti_num(sw_12),
.sel_num(sw_led),
.rstn(rstn),
.seg_ti(digit1),
.seg_one(digit2)
);
seg_sel u5(
.clk_dis(clk_1ms),
.seg_ti(digit1),
.seg_one(digit2),
.digit(digit),
.selone(dis_sel)

);

endmodule