gd32 串口DMA发送&接收不定长数据例程

main.c

/*!
    \file    main.c
    \brief   running LED

    \version 2023-03-31, V1.0.0, firmware for GD32H7xx
*/

/*
    Copyright (c) 2023, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice,
       this list of conditions and the following disclaimer in the documentation
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors
       may be used to endorse or promote products derived from this software without
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

#include "gd32h7xx.h"
#include "systick.h"

#include "string.h"
#include "stdio.h"



__attribute__ ((aligned(32))) uint8_t usart_tx_buff[1024] = {0};
__attribute__ ((aligned(32))) uint8_t usart_rx_buff[1024] = {0};


/*!
    \brief      enable the CPU Chache
    \param[in]  none
    \param[out] none
    \retval     none
*/
static void cache_enable(void)
{
    /* Enable I-Cache */
//    SCB_EnableICache();

    /* Enable D-Cache */
//    SCB_EnableDCache();
}


void usart_init()
{
    rcu_periph_clock_enable(RCU_GPIOB);
    rcu_periph_clock_enable(RCU_USART0);

    nvic_irq_enable(USART0_IRQn, 2, 2);

    gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_6);
    gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_7);

    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_6);

    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_7);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_7);

    usart_deinit(USART0);
    usart_word_length_set(USART0, USART_WL_8BIT);
    usart_stop_bit_set(USART0, USART_STB_1BIT);
    usart_parity_config(USART0, USART_PM_NONE);
    usart_baudrate_set(USART0, 921600U);
    usart_transmit_config(USART0, USART_TRANSMIT_ENABLE);
    usart_receive_config(USART0, USART_RECEIVE_ENABLE);
    usart_interrupt_enable(USART0, USART_INT_IDLE);
    usart_enable(USART0);
}

void usart_transmit(char* buff, int size)
{
    for (int i = 0; i < size; ++i) {
        usart_data_transmit(USART0, buff[i]);
        while (RESET == usart_flag_get(USART0, USART_FLAG_TBE)) {}
    }
}


void usart_transmit_dma(char* buff, int size)
{
    memcpy(usart_tx_buff, buff, size);
    dma_memory_address_config(DMA0, DMA_CH0, DMA_MEMORY_0, usart_tx_buff);
    dma_transfer_number_config(DMA0, DMA_CH0, size);
    dma_channel_enable(DMA0, DMA_CH0);
}

void led_init()
{
    rcu_periph_clock_enable(RCU_GPIOJ);

    gpio_mode_set(GPIOJ, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_8);
    gpio_output_options_set(GPIOJ, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_8);

    gpio_mode_set(GPIOJ, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
    gpio_output_options_set(GPIOJ, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_9);

    gpio_bit_set(GPIOJ, GPIO_PIN_8);
    gpio_bit_set(GPIOJ, GPIO_PIN_9);

}


void dma_config()
{
    rcu_periph_clock_enable(RCU_DMA0);
    rcu_periph_clock_enable(RCU_DMAMUX);
    nvic_irq_enable(DMA0_Channel0_IRQn, 2, 0);
    nvic_irq_enable(DMA0_Channel1_IRQn, 2, 1);

    dma_single_data_parameter_struct dma_init_struct;

    //TX
    dma_deinit(DMA0, DMA_CH0);
    dma_single_data_para_struct_init(&dma_init_struct);
    dma_init_struct.request      = DMA_REQUEST_USART0_TX;
    dma_init_struct.direction    = DMA_MEMORY_TO_PERIPH;
    dma_init_struct.memory0_addr  = (uint32_t)usart_tx_buff;
    dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
    dma_init_struct.number       = 1;
    dma_init_struct.periph_addr  = (uint32_t)(&USART_TDATA(USART0));
    dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
    dma_single_data_mode_init(DMA0, DMA_CH0, &dma_init_struct);

    dma_circulation_disable(DMA0, DMA_CH0);
    usart_dma_transmit_config(USART0, USART_TRANSMIT_DMA_ENABLE);
    dma_interrupt_enable(DMA0, DMA_CH0, DMA_INT_FTF);
//    dma_channel_enable(DMA0, DMA_CH0);

    //RX
    dma_deinit(DMA0, DMA_CH1);
    dma_single_data_para_struct_init(&dma_init_struct);
    dma_init_struct.request      = DMA_REQUEST_USART0_RX;
    dma_init_struct.direction    = DMA_PERIPH_TO_MEMORY;
    dma_init_struct.memory0_addr  = (uint32_t)usart_rx_buff;
    dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
    dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
    dma_init_struct.number       = 1024;
    dma_init_struct.periph_addr  = (uint32_t)(&USART_RDATA(USART0));
    dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
    dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
    dma_single_data_mode_init(DMA0, DMA_CH1, &dma_init_struct);

    dma_circulation_disable(DMA0, DMA_CH1);
    usart_dma_receive_config(USART0, USART_RECEIVE_DMA_ENABLE);
    dma_interrupt_enable(DMA0, DMA_CH1, DMA_INT_FTF);
    dma_channel_enable(DMA0, DMA_CH1);
}


void DMA0_Channel0_IRQHandler()
{
    if (RESET != dma_interrupt_flag_get(DMA0, DMA_CH0, DMA_INT_FLAG_FTF)) {
        dma_interrupt_flag_clear(DMA0, DMA_CH0, DMA_INT_FLAG_FTF);


        gpio_bit_toggle(GPIOJ, GPIO_PIN_8);
    }
}

void DMA0_Channel1_IRQHandler()
{
    if (RESET != dma_interrupt_flag_get(DMA0, DMA_CH1, DMA_INT_FLAG_FTF)) {
        dma_interrupt_flag_clear(DMA0, DMA_CH1, DMA_INT_FLAG_FTF);

        memcpy(usart_tx_buff, usart_rx_buff, 1024);
        usart_transmit_dma(usart_tx_buff, 1024);


        dma_single_data_parameter_struct dma_init_struct;
        dma_deinit(DMA0, DMA_CH1);
        dma_single_data_para_struct_init(&dma_init_struct);
        dma_init_struct.request      = DMA_REQUEST_USART0_RX;
        dma_init_struct.direction    = DMA_PERIPH_TO_MEMORY;
        dma_init_struct.memory0_addr  = (uint32_t)usart_rx_buff;
        dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
        dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
        dma_init_struct.number       = 1024;
        dma_init_struct.periph_addr  = (uint32_t)(&USART_RDATA(USART0));
        dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
        dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
        dma_single_data_mode_init(DMA0, DMA_CH1, &dma_init_struct);

        dma_circulation_disable(DMA0, DMA_CH1);
        usart_dma_receive_config(USART0, USART_RECEIVE_DMA_ENABLE);
        dma_interrupt_enable(DMA0, DMA_CH1, DMA_INT_FTF);
        dma_channel_enable(DMA0, DMA_CH1);

        gpio_bit_toggle(GPIOJ, GPIO_PIN_9);
    }
}

void USART0_IRQHandler()
{
    if (RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_IDLE)) {
        usart_interrupt_flag_clear(USART0, USART_INT_FLAG_IDLE);

        uint32_t size = 1024U - dma_transfer_number_get(DMA0, DMA_CH1);
        memcpy(usart_tx_buff, usart_rx_buff, size);
        usart_transmit_dma(usart_tx_buff, size);

        dma_single_data_parameter_struct dma_init_struct;
        dma_deinit(DMA0, DMA_CH1);
        dma_single_data_para_struct_init(&dma_init_struct);
        dma_init_struct.request      = DMA_REQUEST_USART0_RX;
        dma_init_struct.direction    = DMA_PERIPH_TO_MEMORY;
        dma_init_struct.memory0_addr  = (uint32_t)usart_rx_buff;
        dma_init_struct.memory_inc   = DMA_MEMORY_INCREASE_ENABLE;
        dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
        dma_init_struct.number       = 1024;
        dma_init_struct.periph_addr  = (uint32_t)(&USART_RDATA(USART0));
        dma_init_struct.periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
        dma_init_struct.priority     = DMA_PRIORITY_ULTRA_HIGH;
        dma_single_data_mode_init(DMA0, DMA_CH1, &dma_init_struct);

        dma_circulation_disable(DMA0, DMA_CH1);
        usart_dma_receive_config(USART0, USART_RECEIVE_DMA_ENABLE);
        dma_interrupt_enable(DMA0, DMA_CH1, DMA_INT_FTF);
        dma_channel_enable(DMA0, DMA_CH1);

        gpio_bit_toggle(GPIOJ, GPIO_PIN_9);
    }
}


/*!
    \brief      main function
    \param[in]  none
    \param[out] none
    \retval     none
*/
int main(void)
{
    /* enable the CPU Cache */
    cache_enable();
    /* configure systick */
    systick_config();

    led_init();
    usart_init();


    dma_config();

    char msg[] = "Hello World\r\n";
    usart_transmit_dma(msg, strlen(msg));




    while(1) {

        delay_1ms(100);
    }
}