hdlbits Cs450/gshare

最新推荐文章于 2024-08-22 17:42:47 发布

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最新推荐文章于 2024-08-22 17:42:47 发布

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文章标签： fpga开发 verilog

本文链接：https://blog.csdn.net/weixin_43475286/article/details/132048112

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Cs450/counter 2bc

根据state大小判断拿的程度。

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
//00没拿，01weak没拿，10weak拿了，11拿了
    always@(posedge clk or posedge areset)
        if(areset)
            state<=2'b01;
    else if(train_valid & train_taken) //拿了+1
        if(state==2'd3)
            state<=state;
        else
        	state<=state+2'b1;
    else if(train_valid & ~train_taken)//没拿-1
        if(state==0)
        	state<=state;
        else
            state<=state-2'b1;
        
endmodule

Cs450/history shift

判断是否拿预测值。

module top_module(
    input clk,
    input areset,

    input predict_valid,
    input predict_taken,
    output [31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);

    always@(posedge clk or posedge areset)
        if(areset)
            predict_history<=0;
    	else if(train_mispredicted)
            predict_history<={train_history[30:0],train_taken}; //预测错误，实际输入
        else if(predict_valid)
        	predict_history<={predict_history[30:0],predict_taken};//预测正确，用预测值

endmodule

Cs450/gshare

train_taken决定PTH里的值加或者减。//2‘b11 taken 2‘b10 weak-taken 2‘b01 weak-not-taken 2‘b00 not-taken；
train_valid决定用train_history[5:0],train_taken；
predict_valid决定用predict_history[5:0],PHT高位；

PTH的输入输出

module top_module(
    input clk,
    input areset,

    input  predict_valid,
    input  [6:0] predict_pc,
    output predict_taken,
    output [6:0] predict_history,

    input train_valid,
    input train_taken,
    input train_mispredicted,
    input [6:0] train_history,
    input [6:0] train_pc
);
    //11 taken 10 weak-taken 01 weak-not-taken 00 not-taken
    reg pht1[127:0];//taken
    reg pht0[127:0];//w-taken
    wire [6:0]ad,ad2;

 	assign ad=train_history^train_pc;
 	assign ad2=predict_history^predict_pc;
    integer i;
    always@(posedge clk or posedge areset)
        if(areset)
            for (i=0; i<128; i=i+1) begin 
                pht1[i] <= 1'b0; 
                pht0[i] <= 1'b1; 
            end
    	else if(train_valid & train_taken)begin
        	if({pht1[ad],pht0[ad]}==2'b11)
            	{pht1[ad],pht0[ad]}<=2'b11;
        	else
        		{pht1[ad],pht0[ad]}<={pht1[ad],pht0[ad]}+2'b1;  //拿了很多次
   	 	end
    	else if(train_valid & ~train_taken)begin
        	if({pht1[ad],pht0[ad]}==0)
        		{pht1[ad],pht0[ad]}<=0;
        	else
            	{pht1[ad],pht0[ad]}<={pht1[ad],pht0[ad]}-2'b1;  //拿了次数减少
    	end
     	
    assign predict_taken=pht1[ad2];  //根据pht1[], hash概率taken
    always@(posedge clk or posedge areset)
        if(areset)
            predict_history<=7'b0;
    	else if(train_valid&train_mispredicted)
            predict_history<={train_history[5:0],train_taken};//用计算结果
        else if(predict_valid)
            predict_history<={predict_history[5:0],predict_taken};//用预测结果
    	
endmodule