verilog技巧篇
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补码位数扩充
补码位数扩充[+1]原 = 0000 0001[-1]原 = 1000 0001[+1] = [00000001]原 = [00000001]反[-1] = [10000001]原 = [11111110]反补码,正数的补码是本身,负数的补码是反码+1。[+1] = [00000001]原 = [00000001]反 = [00000001]补[-1] = [10000001]原 = [11111110]反 = [11111111]补input [14:0] REG_YINCRP;原创 2022-02-09 15:06:01 · 2420 阅读 · 0 评论 -
下降沿触发
always @ (posedge clk or negedge resetn) if (!resetn) r_vsync <= `SD 1'b0; else r_vsync <= `SD vsync;wire vsync_fe = (!vsync)&r_vsync;always @ (posedge clk or negedge resetn)begin if (!resetn) xxxx; els原创 2021-06-03 14:22:23 · 1232 阅读 · 0 评论