Circuits--Sequential Logic--Finite State Machines--Fsm1s

网址：https://hdlbits.01xz.net/wiki/Fsm1s

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter		A = 1'b0;
    parameter		B = 1'b1;

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) 
            begin  
            // Fill in reset logic
           		present_state <= B; 
        	end 
        else
            begin
                present_state <= next_state;
            end
    end
                
        always@(*)   begin
            case (present_state)
                // Fill in state transition logic
            	A:
                    begin
                        if(in == 1'b1)
                            next_state <= A;
                        else
                            next_state <= B;
                    end
                B:
                    begin
                        if(in == 1'b1)
                            next_state <= B;
                        else
                            next_state <= A;
                    end
                default:
                    next_state <= B;
            endcase
        end
    
    //assign out = (present_state == A)?0:1;
    assign	out = (present_state == B);


endmodule