网址:https://hdlbits.01xz.net/wiki/Countslow
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)begin
if(reset == 1'b1)
q = 4'd0;
else if(q == 4'd9 && slowena == 1'b1)
q = 4'd0;
else if(slowena == 1'b0)
q = q;
else
q = q + 4'd1;
end
endmodule