HDLBits Practice

HDLBits Practice

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More Verilog Features

1. Condition temary operator ，获得最小值Min；

A Bit of Practice： Unsigned numbers can be compared with standard comparison operators (a < b).Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit.

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

	wire[7:0] comp1,comp2;
	assign comp1 = a < b ? a : b ;
	assign comp2 = comp1 < c ? comp1 : c ;
    assign min = comp2 < d ? comp2 : d;

endmodule

2. Reduction ,获得奇偶检验值，每⼀位分别异或

A Bit of Practice：We will use “even” parity, where the parity bit is just the XOR of all 8 data bits.

module top_module (
    input [7:0] in,
    output parity); 
	integer i;
	reg tmp;
	always@(*)begin
		tmp = in[0];
		for(i = 1;i<8;i = i+1)
			tmp = in[i] ^ tmp;
	end
	assign parity = tmp;
endmodule

3. Reduction：Even wider gates ,获得100个参数的3种组合结果

AND,OR,XOR

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
	integer i;
	reg out_and_tmp;
	reg out_or_tmp;
	reg out_xor_tmp;
	always@(*)begin
		out_and_tmp = in[0];
		out_or_tmp = in[0];
		out_xor_tmp = in[0];
		for(i = 1;i <100;i = i + 1 )
		begin
			out_and_tmp = in[i] & out_and_tmp;
			out_or_tmp = in[i] | out_or_tmp;
			out_xor_tmp = in[i] ^ out_xor_tmp;
		end
	end
	assign out_and = out_and_tmp;
	assign out_or = out_or_tmp;
	assign out_xor = out_xor_tmp;
endmodule

4. Vector100r ,获得100个参数的反转值

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module( 
    input [99:0] in,
    output [99:0] out
);
	reg[99:0] out_reg;
	integer i;
	always@(*) begin
		for(i = 0;i<100;i = i+1)
			out_reg[i] = in[99-i];
	end
	assign out = out_reg;
endmodule

5. Popcount255 ,在255个数据中，获取1 的次数

A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module( 
    input [254:0] in,
    output [7:0] out );
	
    reg[7:0] count;
	integer i;
	
	always@(*) begin
		count = 8'd0;
		for(i = 0; i < 255 ;i = i + 1)
			if(in[i])
				count = count + 1;
			else
				count = count;
	end
	
	assign out = count;
endmodule

6. Adder100i ,计算100个加法器的计算结果

To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder.

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
	
	reg[99:0] sum_reg;
	reg[99:0] cout_reg;
	
	integer i;
	always@(*)begin
		for(i = 0; i < 100 ;i = i + 1)
			if(i == 0)
				{cout_reg[0],sum_reg[0]} = a[0] + b[0] + cin;
			else
				{cout_reg[i],sum_reg[i]} = a[i] + b[i] + cout_reg[i-1];
			
	end
	assign cout = cout_reg;
	assign sum = sum_reg;
endmodule

7. Bcdadd100 ,计算100个bcd模块的加法结果

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
	
	reg[399:0] cout_reg;
	reg[399:0] sum_reg;
	genvar i ;
	generate
            for(i = 0; i<400 ;i = i + 4)begin : bcdadd100  
                if(i == 0) begin 
                    bcd_fadd bcd_fadd_inst(
                        .a(a[3:0]),
                        .b(b[3:0]),
                        .cin(cin),
                        .cout(cout_reg[0]),
                        .sum(sum_reg[3:0]) );
                    end
                else begin
                    bcd_fadd bcd_fadd_inst(
                        .a(a[i+3:i]),
                        .b(b[i+3:i]),
                        .cin(cout_reg[i-4]),
                        .cout(cout_reg[i]),
                        .sum(sum_reg[i+3:i]) );
                end
            end
	endgenerate
	assign sum = sum_reg;
    assign cout = cout_reg[400-4];
	
endmodule