HDLBits Practice-Basic Gates-Multiplexers

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已于 2023-09-09 15:37:21 修改

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于 2023-09-09 15:29:08 首次发布

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Verilog Language

HDLBits Practice

HDLBits Practice

1.Gatesv : out_both,out_any,out_different

You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour.

module top_module( 
    input [3:0] in,
    output reg[2:0] out_both,
    output reg[3:1] out_any,
    output reg[3:0] out_different );

	integer i;
	always@(*)begin
		for(i = 0; i < 4 ;i = i + 1) begin
			if(i<3)
				if(in[i] == 1 && in[i+1] == 1) 
					out_both[i] = 1'b1;
				else
					out_both[i] = 1'b0;
			else	
				out_both = out_both;
            if(i != 0)
                if(in[i] == 1 || in[i-1] == 1)
					out_any[i] = 1'b1;
				else
					out_any[i] = 1'b0;
			else
				out_any = 0;
			if(i == 3)
				if(in[3] != in[0])
                    out_different[3] = 1'b1;
				else
                    out_different[3] = 1'b0;
			else
				if(in[i] != in[i+1]) 
					out_different[i] = 1'b1;
				else
					out_different[i] = 1'b0;
				
		end
	end
endmodule

2.Gatesv100

ou are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour.

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );

	integer i;
	always@(*)begin
		for(i = 0; i < 100 ;i = i + 1) begin
			if(i<99)
				if(in[i] == 1 && in[i+1] == 1) 
					out_both[i] = 1'b1;
				else
					out_both[i] = 1'b0;
			else	
				out_both = out_both;
			if(i>0)
				if(in[i] == 1 || in[i-1] == 1)
					out_any[i] = 1'b1;
				else
					out_any[i] = 1'b0;
			else
				out_any = out_any;
			if(i == 99)
				if(in[99] != in[0])
					out_different[99] = 1'b1;
				else
					out_different[99] = 1'b0;
			else
				if(in[i] != in[i+1]) 
					out_different[i] = 1'b1;
				else
					out_different[i] = 1'b0;
				
		end
	end
endmodule

3.Mux2to1v :100-bit wide

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	
	genvar i;
	generate 
		for(i = 0; i<100 ;i = i+1) begin: mux2_1
			mux2_1 mux2_1_inst( .a(a[i]), .b(b[i]), .sel(sel),.out(out[i]) ); 
		end
	endgenerate
	
endmodule

module mux2_1(
    input a, b, sel,
    output out ); 
	
assign out = sel ? b: a;

endmodule