szuEDA复试第四套

第二题

第四题
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mulmath is
port{a,b:in std_logic;
c,d:out std_logic};
end mulmath;
architecture math of mulmath is begin
c<=a and b;
c<=a or b;
c<=a + b;
c<=a - b;
d<=not(a);
end math;
第五题
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity highresis is
port{a,c: in std_logic;
x:out std_logic};
end highresis;
architecture high of highresis is begin

process(a,c) begin
if c=‘1’ then
x<=a;
else
x<‘z’;
end if;
end process;
end high;