电路
香茄子
这个作者很懒,什么都没留下…
展开
-
Verilog Syntax
Basic-6'd3; // negative numberx // x unknown or don't care, z or? high impedence(unconnected)-6'd3_3; // _ allowed anywhere in number -》 readablewire a; // 1 bit defaultreg signed [63:0] a; // ...原创 2020-01-22 03:08:45 · 390 阅读 · 0 评论 -
Analog Circuit
Note of Analog CircuitBook: Microelectronic Circuits by Sedra SmithNorton and Thevenin CircuitFind Equivalent ReqR_{eq}Req:Apply test source VTV_TVTMeasure test current ITI_TITReqR_{eq}Req ...原创 2019-02-19 14:52:02 · 1411 阅读 · 0 评论