Verilog Syntax

Notes when I learned Verilog

Basic

-6'd3;	// negative number

x	// x unknown or don't care, z or? high impedence(unconnected)
-6'd3_3;	// _ allowed anywhere in number －》 readable

wire a;	// 1 bit default
reg signed [63:0] a;	// reg retain value until another value is placed
reg	[0:40] vm;	// vm[0] is most significant bit

a[31-:8];	// a[31:24]
vm[<