RRAM/ Near Memory Computing (NMC) Survey - Reading Notes 0706

Reading Notes for Resistive Random Access Memory – Day 1

Chapter 1 Introduction to RRAM Technology

The ideal characteristics of a memory device:

measures	value
write/read speed	< ns
operation voltage	< 1V
energy consumption	~ fJ/bit for write/read
data retention time	> 10 years
write/read cycling endurance	> $10^{17}$ cycles
scalability	< 10 nm

STT-MRAM: spin-transfer-torque magnetoresistive random access memory

PCRAM: phase change random access memory

RRAM: resistive random access memory

They are non-volatile two-terminal devices, they differentiate their states by switching between a high resistance state (HRS, or off-state) and a low resistance state (LRS, or off-state). The transition between the two states can be triggered by electrical inputs.

The detailed switching physics:

• STT-MRAM: difference in resistance between the parallel configuration (corresponding to LRS) and the anti-parallel configuration (corresponding to HRS) of two ferromagnetic（铁磁性的） layers separated by a thin tunneling insulator layer.
• PCRAM: relies on chalcogenide（氧属化物，硫族化物）material to switch between the crystalline phase（LRS） and the amorphous phase（HRS）
• RRAM: relies on the formation（LRS）and the rupture（破裂态，HRS）of conductive filaments（导电丝）in the insulator（绝缘体）between two electrodes（电极）.

There are two types of RRAM:

• based on conductive filaments consisting of oxygen vacancies（空穴）, which is typically referred to as oxide-based RRAM
• based on conductive filaments consisting of metal atoms, which is also called conductive-bridge RAM（CBRAM）

Despite different underlying switching physics, they share a lot of common device characteristics and the array architecture design considerations are very similar.

Concepts and Terminologies:

• Metal-Insulator-Metal structure of RRAM

• The switching event from HRS to LRS is called the “set” process

• The switching event from LRS to HRS is called the “reset” process

• Usually for the fresh samples, the initial resistance is very high and a large voltage is needed for the first cycle to trigger the switching behaviours for the subsequent cycles. This is called the “forming” process.

• The switching modes of RRAM can be broadly classified into two switching modes: unipolar and bipolar.

  • Unipolar switching means the switching direction depends on the amplitude of the applied voltage but not on the polarity of the applied voltage. （意思是，在两个方向加电压都可以获得"set"和"reset"的效果）. If the unipolar switching can symmetrically occur at both positive and negative voltages, it is also referred to as a nonpolar switching mode.
  • Bipolar switching means the switching direction depends on the polarity of the applied voltage. Thus set can only occur at one polarity and reset can only occur at the reversed polarity.

• To read the data from the cell, a small read voltage that does not affect the memory state is applied to detect whether the cell is in HRS or LRS.

• The switching mode is not an intrinsic property of the oxide itself but a property of both the oxide materials and the eletrode/oxide interface.

• Generally, the unipolar switching needs a higher reset current than the bipolar switching, and shows a larger variability as well. Therefore, today RRAM research and development focus more on the bipolar switching.

小结：

Recent Researches:

• Device sizes down to 10nm or below have been demonstrated [28, 30]

• programming current is now in the order of tens of uA or a few uA

• programming speed is in the order of tens of ns or a few ns

• programming endurance cycles are typically larger than $10^6$ with a record up to $10^{12}$ [31]

• retention time is > 3000 h at 150 ${}^{\circ }$C and extrapolated to be more than 10 years at 85 ${}^{\circ }$C

• the forming process can be eliminated by shrinking the oxide thickness or other oxide stack engineering strategies.

• Most of these good characteristics were reported in HfOx or TaOx systems.

• Demonstrations of 2-bits and 3-bits multi-level operation have also been made [33, 34]

• Chip-level RRAM array macro from 4MB to 32 Gb capacity with peripheral circuitry have been demonstrated by industry as well [35, 36, 37]

Chapter 2 RRAM Device Fabrication and Performance

Device Fabrication: Forming-Free and Scalability

To deposit the resistive switching oxide layer, two typical methods are used:

(1) physical vapor deposition (PVD) : sputter from metal targets followed by annealing in oxygen ambient（在含氧环境下退火）or reactive sputtering in ambient, room temperature

(2) atomic layer deposition (ALD) : from metal-organic precursor in water or ozone ambient, 200 ${}^{\circ }$C

This Chapter: user IMEC device（TiN/Hf/HfOx/TiN） to illustrate RRAM cell design and its impact on the forming behavior.

The IMEC devices are based on 65nm silicon CMOS process and built on top of a transistor’s drain contact via.

What we learned from it:

• HfOx thickness and Hf capping layer thickness affect the device characteristics (especially the forming behaviours)

• Forming voltage is a strong function of the device area (like the soft-breakdown of dielectric, the breakdown voltage depends on the number of defects rather than the defect density in the dielectric layer, as we scale down, the number of defacts went down, so we need more voltage to form a conductive filament)

• poly-crystalline（多晶的）HfOx has a lower forming voltage than the amorphous（非晶的）HfOx probably due to the leakage through the grain（晶粒）boundaries.

• To reduce the forming Voltage, reduce the HfOx layer thickness is a better approach.

• 10nm HfOx layers: 5.3V；5nm HfOx layers: 2.3V；2nm HfOx layers: forming-free（both forming voltage and set voltage in the subsequent cycles < 1V）但是太薄了容易短路，需要TiN电极&氧化物生长最够平坦（tradeoff）

• a thicker metal capping layer can reduce the forming voltage, because it attract more oxygen from the oxide layer and make the oxide thickness and make the oxide lay more oxygen deficient.

• reducing oxide thickness and increasing the initial defect density by thicker metal capping layer may also severely derease the resistivity of the oxide layer and sacrifice the memory on/off ratio. （开关电流比，决定此位存的是0还是1，会严重影响错误率）

sub-10nm devices have been successfully fabricated

在RRAM formed之后的cycles中，switching仅仅在一个很小的region中进行，大约几十nm到几nm，取决于LRS上的电流。在filament的方向上，active region同样很小，as the filament is only partially ruptured.

Device Performance

programming speed

• programming speed is a strong function of programming voltage（as voltage went down, Pulse Duration went up）, Increasing about 0.25V and 0.5V of programming voltage will increase the programming speed by one order of magnitude for 1um cell and 10nm cell, respectively.
• using very large voltage can cause damage to the device
• The instrinsic RRAM switching speed limit may be lower than tens of ps. （很难被测量）

variability of device

The variations include temporal (cycle to cycle) variations and spatial (device to device) variations. The spatial variations may be improved with the precise manufacturing control of uniformity accross wafer. However, the temporal variations seem an intrinsic property of the RRAM switching dynamics caused by the stochastic nature of the oxygen vacancies generation and migration processes.

The HRS resistance variation is more ramarkable than the LRS.

multi-level cell (MLC)

modulate the resistance states into multi-levels to realize the MLC operation. 也就是说，不仅仅有HRS和LRS两种状态，可以有更多的中间状态。

• controlling the set compliance current
• controlling reset voltage

requires a very tight control of the resistance distribution to distinguish between levels.

a write-verify programming scheme is used to tighten the resistance distribution for MLC, but sacrifice the programming speed. as an example, single-level cell(SLC) can achieve 7.2ns programming speed, while MLC (2bits/cell) needs 160 ns to perform the write-verify scheme.

Device Reliability

Reliability of RRAM has two aspects: cycling edurance and data retention

cycling edurance:

• A weak set condition / strong reset condition tends to result in a set failure after $10^6$ cycles
• A strong set condition / weak reset condition tends to result in a reset failure after $10^6$ cycles

A balanced set/reset condition is important to improve the cycling endurance.

optimal for IMEC’s HfOx-based RRAM: set: WL=1V, BL=1.8V, width=5ns; reset: WL=3V, SL=1.8V, width=10ns.

A stable 15$\times$ on/off ratio could be achieved for $10^{10}$ cycles.

RRAM目前做到最大的cycling endurance是$10^{12}$cycles, 基于TaOx. 相比其他的, RRAM这个已经足够高了.

Note: Ta 钽 tǎn

data retention:

Typically, data retention time longer than 10 years at thermal stress up to 85${}^{\circ }$C is expected for NVM applications.

有两种方法测量, 一种是保持温度, 每隔一段时间测一次电压, 然后线性延拓到相交的位置(一般在10年后). 这种方法的局限性在于, 线性延拓到那么长, 稍微有点非线性就差好多出去; 另一种方法是, 将器件加热到很高的温度, 这时器件的retention已经可以忍受了, 比如10天, 30天. 画出retention随温度变化的曲线, 再延伸到85${}^{\circ }$C得到结果.

a lower compliance current results in worse LRS data retention, because a weaker filament tends to rupture easily under high temperature. A trade-off between low power operation and the long data retention

data retention can also because worse as more cycles have been programmed. So the data retention characterization should be combined with the endurance characterization.

Chapter 3 RRAM Characterization and Modeling

Overview of RRAM Physical Mechanism

The resistive switching is associated with the generation of oxygen vacancies (Vo) and migration of oxygen ions ($O^{2-}$) to form conductive filament or filaments between the two eletrodes.

This process is also referred to as the redox (reduction/ oxidation) effect.

We will focus on the filamentary switching mechanism, which is the prevailing theory for most of the metal-oxide RRAM. (non-filamentary or interfacial barrier modulation mechanism, refer to [48])

A general physical picture:

Initially, the Vo density is low. Under the high electric field (> 10MV/cm), the oxygen atoms are knocked out of the lattice, and become $O^{2-}$ drifting toward the anode(阳极) and Vo are left in the oxide layer. $O^{2-}$ are discharged as neutral non-lattice oxygen if the anode materials are noble metals(惰性) or react with the oxidizable anode materials to form an interfacial oxide layer.