2021-08-17_this is the fifth component in a series of five ex-CSDN博客

本文链接：https://blog.csdn.net/weixin_44573736/article/details/119766547

该博客介绍了一个基于有限状态机（FSM）的定时器设计，该定时器在检测到特定序列1101后启动，接着使能shift_ena信号4个周期，然后开始计数并等待计数完成。当接收到done_counting信号时，它通知用户计时已结束，并在接收到ack信号后重置以寻找下一个启动序列。FSM的状态转换图详细描述了这一过程，包括如何在不同状态下响应输入和输出信号。

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This is the fourth component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.

We want to create a timer that:

is started when a particular pattern (1101) is detected,
shifts in 4 more bits to determine the duration to delay,
waits for the counters to finish counting, and
notifies the user and waits for the user to acknowledge the timer.
In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.

The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.

After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.

At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The state machine should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The ‘x’ states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.
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相信做了这道题前面几个小练习的小伙伴再做这道题一点也不难，大概就是把前面的几个部分加起来了，首先检测一个1101的序列，然后shift_ena使能四个周期，之后就是count和done的设置了，状态图如下图所示。图中最后一部应该回到A的跨度太大了，没往回去画，你们理解就好。
在这里插入图片描述
下面展示一些 内联代码片。


module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    parameter A=0,B=1,C=2,D=3,E=4,F=5,G=6,H=7,I=8,J=9;
    reg [3:0]state,n_state;
    //状态转化
    always@(posedge clk)begin
        if(reset)begin
            state <= A;
        end
        else begin
            state <= n_state;
        end
    end
    //状态转化的条件，A-D为1101序列检测，E-F为四个使能置1周期
    always@(*)begin

        case(state)
            A: n_state = data? B:A;
            B: n_state = data? C:A;
            C: n_state = data? C:D;
            D: n_state = data? E:A;
            E: n_state = F;
            F: n_state = G;
            G: n_state = H;
            H: n_state = I;
            I: n_state = done_counting? J:I;
            J: n_state = ack? A:J; 

        endcase
    end
    
    assign shift_ena = (state==E)||(state==F)||(state==G)||(state==H);
    assign counting = state==I;
    assign done = state==J;

endmodule