2021-08-17

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

下面展示一些 内联代码片。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    parameter A=0,B=1,C=2,D=3,E=4;
    reg [2:0]state,n_state;
    always@(posedge clk)begin
        if(reset)begin
            state <= A;
        end
        else begin
            state <= n_state;
        end
    end
    always@(*)begin
        case(state)
            A: n_state = data? B:A;
            B: n_state = data? C:A;
            C: n_state = data? C:D;
            D: n_state = data? E:A;
            E: n_state = E;
        endcase
    end
    assign start_shifting = state==E;
    
    

endmodule