Verilog HDL：PCM解码器设计（Testbench5）

PCM_DECODER_TEST_5.v

/********************************************************************************* 
  *Copyright(C), IC Design
  *FileName: PCM_DECODER_TEST_5.v
  *Author: Yue Shipeng
  *Version: 6.0
  *Date: 2023.01.21 03:00
  *Description: TESTBENCH FOR PCM_DECODER
  *History: Notepad++ version
**********************************************************************************/  

/********************************************************************************* 
PCM DECODER TEST 5
**********************************************************************************/

`timescale 10ns/1ns

module PCM_DECODER_TEST_5;

reg clk;
reg rst;
reg din;
wire [7:0] dout;
wire D_en;
wire F_en;

parameter half_cycle = 10;

PCM_DECODER ut5(
	.clk(clk),
	.rst(rst),
	.din(din),
	.dout(dout),
	.D_en(D_en),
	.F_en(F_en)
);

initial begin
	clk = 0;
	forever begin
		clk = # half_cycle ~ clk;
	end
end

initial begin
	rst = 1;
	# (1 * half_cycle) rst = 0;
	# (2 * half_cycle) rst = 1;
end

initial begin

	// the initial set of din;
	din <= 0;
	
	// the SOF generation;
	repeat (4) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (160) @ (posedge clk);
	din <= 1;
	
	// the 3 Byte data generation;
	
	// 5E, 0101_1110;
	wave_10();
	wave_11();
	wave_01();
	wave_01();
	
	// 6F, 0110_1111;
	wave_11();
	wave_11();
	wave_10();
	wave_01();
	
	// 7A, 0111_1010;
	wave_10();
	wave_10();
	wave_11();
	wave_01();

	// the EOF generation;
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (32) @ (posedge clk);
	din <= 0;
	
	repeat (20) @ (posedge clk);
	$finish;
end

initial begin
	$fsdbDumpfile("./verdiFsdb/PCM_DECODER_TEST_5.fsdb");
	$fsdbDumpvars(0);
end

// the 00 generation;
task wave_00();
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (128) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 1;
endtask

// the 01 generation;
task wave_01();
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (96) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (48) @ (posedge clk);
	din <= 1;
endtask

// the 10 generation;
task wave_10();
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (96) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 1;
endtask

// the 11 generation;
task wave_11();
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (64) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (48) @ (posedge clk);
	din <= 1;
endtask

endmodule

Experiment Result