白码王子小张的博客

本文详细介绍了Vivado 布局Place Design报错: [DRC REQP-1741] IDELAY3 drivers invalid load :IDELAY3 data_progress_U0/u_delay_rxd DATAOUT pin(net: data_progress_U0/data_clk)may not drive a BUFG*的原因及解决方法

本文详细介绍了Vivado报错解决：[DRC NSTD-1] Unspecified I/O Standard: 13 out of 175 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’和[DRC UCIO-1] Unconstrained Logical Port: 13 out of 175 logical ports have no user assigned specific location constraint (LOC)

本文详细介绍了Vivado 在Block Design中调用自定义封装的IP核后Generate Output Product时报错：[IP_Flow19-3478]Validation failed fo rparameter CoeFile(Coe_File) with value ../xxx/xxxxxx/.coe' for IP system_system_top_0_o/bik_mem_gen_1. Invalid Coe File-Unable to open the file的解决方法.

本文详细介绍了Vivado 在Block Design添加PL模块时报错：The xilinx.com:ip:XXXXX core does not support module refer的原因及解决方法.

本文详细介绍了将Simulink HDL Coder综合生成的Vivado工程的信号连接到LED引脚验证设计是否正常工作，Vivado布局布线时出现报错: [Common 17-69] Command failed: Placer could not place all instances的解决方法.

本文详细介绍了vivado程序固化到Flash报错: Vivado程序固化到Flash时报错：[Labtools 27-3347] Flash Programming Unsuccessful: Byte 169320 does not match (00 != B2)的解决方法。