一,实验要求;通过数码管进行秒的个位,秒的十位,分的个位,分的十位的时钟显示。
二,总体思路:
用PLL锁相环分频把20Mhz的信号分频为2Mhz,然后在通过计数器把2Mhz的频率分频为1hz,1hz就是1秒,然后进行计数,计数完以后通过60进制的BCD码,然后通过4选一的数据选择器把数据进行存取,存取完以后然后通过数码管的译码逻辑进行数码显示,显示完以后为了进行位选,在通过分频器进行分频,通过人的视觉暂留,让四个数码管同时显示,进行秒的个位,十位,分的个位显示。
三,各模块的功能
1,分频:通过PLL锁相环将系统的20Mhz分频为2Mhz
2,然后在通过一个计数器将2MHZ分频为1HZ,
3,分频为1HZ以后进行计数,1HZ就是1秒,计数器
程序如下:
ENTITY CTR60 IS
PORT(
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C : OUT STD_LOGIC);
END ENTITY CTR60;
ARCHITECTURE behav OF CTR60 IS
BEGIN
PROCESS(CLK)
VARIABLE count :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF CLK’EVENT AND CLK=‘1’ THEN
IF count(3 DOWNTO 0) < 9 THEN
count(3 DOWNTO 0) := count(3 DOWNTO 0)+1;
ELSE
count(3 DOWNTO 0) := “0000”;
count(7 DOWNTO 4) := count(7 DOWNTO 4)+1;
END IF;
IF count(7 DOWNTO 4) > 5 THEN
count(7 DOWNTO 0) := “00000000”;
C <= ‘1’;
ELSE
C <= ‘0’;
END IF;
END IF;
Q <= count;
END PROCESS;
END;
4,进行计数以后通过4选一数据选择器将数据进行存取
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX41A IS
PORT (a, b, C,d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ;
END ENTITY MUX41A;
ARCHITECTURE BHV OF MUX41A IS
BEGIN
PROCESS (S)
BEGIN
CASE (S) IS
WHEN “00” => Y<=a ;
WHEN “01” => Y<=b ;
WHEN “10” => Y<=C ;
WHEN “11” => Y<=d ;
WHEN OTHERS => NULL ;
END CASE;
END PROCESS;
END BHV ;
5,数码管译码逻辑,共阴数码管显示程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DecoderDemo IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)) ;
END DecoderDemo;
ARCHITECTURE one OF DecoderDemo IS
BEGIN
PROCESS( A )
BEGIN
CASE A IS
WHEN “0000” => LED7S <= “0111111” ;
WHEN “0001” => LED7S <= “0000110” ;
WHEN “0010” => LED7S <= “1011011” ;
WHEN “0011” => LED7S <= “1001111” ;
WHEN “0100” => LED7S <= “1100110” ;
WHEN “0101” => LED7S <= “1101101” ;
WHEN “0110” => LED7S <= “1111101” ;
WHEN “0111” => LED7S <= “0000111” ;
WHEN “1000” => LED7S <= “1111111” ;
WHEN “1001” => LED7S <= “1101111” ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END one;
6,一个数码管可以显示了,接下来进行四个数码管显示,首先先进行分频,通过人眼的视觉暂离,将四个数码管进行位选,模块为:
7,
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECODER_4 IS
PORT(
Ax : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
Yx : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ;
END ENTITY DECODER_4 ;
ARCHITECTURE behav OF DECODER_4 IS
BEGIN
PROCESS (Ax) BEGIN
CASE Ax(1 DOWNTO 0) IS
WHEN “00” => Yx<=“1000” ; – 0
WHEN “01” => Yx<=“0100” ; – 1
WHEN “10” => Yx<=“0010” ; – 2
WHEN “11” => Yx<=“0001” ; – 3
WHEN OTHERS => NULL ; – NULL
END CASE ;
END PROCESS ;
END ARCHITECTURE behav ;
然后将各个模块进行连接,就可以正常显示了。
四,总体原理图模块
四,心得和体会
通过做这个综合实验,我们团队通过解决每一个细节问题,对理论知识理解的更加清晰,增强了实践动手的能力,但是在这个过程中也存在一些问题,在刚开始调试的时候数码管频率显示的比较快,通过进行再次的分频,使得数码管可以正常显示。由此,我们意识到,理论和实践之间存在着一定的差距,也进一步增强了我们对这门课的敬畏之心,从中我们也获得了对这门课一定的认同感。