脉冲同步电路的设计（基于verilog实现）

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
    //step1:将脉冲信号转化成电平信号
    //step2:将该电平信号同步到慢的时钟域，并且监测上下沿
    reg                data_level    ;
    reg                data_sync1    ;
    reg                data_sync2    ;
    reg                data_sync3    ;
    
    //脉冲->电平
    always @(posedge clk_fast or negedge clk_slow) begin
        if(~rst_n)begin
            data_level <= 1'b0;
        end
        else
            data_level <= data_in ? ~data_level : data_level;
    end
    
    //同步信号
    always @(posedge clk_slow or negedge rst_n)begin
        if(!clk_slow) begin
            data_sync1 <= 1'b0;
            data_sync2 <= 1'b0;
            data_sync3 <= 1'b0;
        end
        else begin
            data_sync1 <= data_level;
            data_sync2 <= data_sync1;
            data_sync3 <= data_sync2;
        end
    end
    
    //检测上升沿和下降沿
    assign dataout = (data_sync2 ^ data_sync3) ? 1'b1 : 1'b0;
    
endmodule