![](https://img-blog.csdnimg.cn/20201014180756724.png?x-oss-process=image/resize,m_fixed,h_64,w_64)
verilog
ic小白白白
这个作者很懒,什么都没留下…
展开
-
流水线乘法器的verilog设计
代码】流水线乘法器的verilog设计。原创 2022-07-15 09:35:18 · 1217 阅读 · 0 评论 -
脉冲同步电路的设计(基于verilog实现)
代码】脉冲同步电路的设计(基于verilog实现)原创 2022-07-14 21:57:41 · 958 阅读 · 1 评论 -
Edgecapture
module top_module ( input clk, input reset, input [31:0] in, output [31:0] out); reg [31:0] in_last; //存储上次的值 always @(posedge clk) begin in_last <= in; end always @(posedge clk) be.原创 2021-12-05 11:20:04 · 682 阅读 · 1 评论 -
Exams/m2014 q6b
module top_module ( input [3:1] y, input w, output Y2); parameter A=3'b000, B=3'b001, C=3'b010, D=3'b011, E=3'b100, F=3'b101; reg [3:1] next; always @(*) begin case(y) A: next = w ? A : B; .原创 2021-12-04 17:39:09 · 359 阅读 · 0 评论 -
Exams/2014 q3c
本题其实使用组合逻辑就行,clk时钟用不到module top_module ( input clk, input [2:0] y, input x, output Y0, output z); parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100; reg [2:0] state,next_state; assign state = y; alw.原创 2021-12-04 17:24:18 · 215 阅读 · 0 评论 -
Exams/2014 q3bfsm
module top_module ( input clk, input reset, // Synchronous reset input x, output z); parameter s0 = 3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100; reg [2:0] state, next_state; always @(*) begin .原创 2021-12-04 17:08:06 · 211 阅读 · 0 评论 -
Exams/review2015 fsm
This is the fourth component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.We wa原创 2021-12-04 10:17:20 · 409 阅读 · 0 评论 -
Exams/review2015 fsmshift
module top_module ( input clk, input reset, // Synchronous reset output shift_ena); //记录时钟周期 reg [2:0]cnt ; always @(posedge clk) begin if(reset) cnt <= 0; else if(c.原创 2021-12-03 18:44:48 · 162 阅读 · 0 评论 -
Exams/review2015 fsmseq
module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter idle=0, bit1=1, bit2=2, bit3=3, bit4=4; reg[2:0] state, next_state; always @(*) begin .原创 2021-12-03 17:25:58 · 246 阅读 · 0 评论 -
verilog实现1101序列检测器
第一种使用摩尔型有限状态机`timescale 1ns / 1psmodule sequence( input in, input clk, input reset, output check); //同步置位---reset //实现1101序列的检测器 //定义状态 parameter idle=0, bit1=1, bit2 =2, bit3=3, bit4=4; reg [2:0] state, next_st原创 2021-12-03 14:40:15 · 3178 阅读 · 0 评论 -
Exams/review2015 shiftcount
module top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always @(posedge clk) begin if(shift_ena) begin //移位 q &原创 2021-12-03 11:08:48 · 189 阅读 · 0 评论 -
Bugs case
module top_module ( input [7:0] code, output reg [3:0] out, output reg valid=1 );// always @(*) case (code) 8'h45: begin out = 0; valid = 1; end 8'h16: begin out = 1; valid = 1; end 8'h1e: begin原创 2021-12-03 09:41:44 · 608 阅读 · 0 评论 -
Bugs addsubz
有两点注意:1,result_is_zero判断有误2,在out!=0时,要将result_is_zero置零,可以使用else语句,或者赋初始值。// synthesis verilog_input_version verilog_2001module top_module ( input do_sub, input [7:0] a, input [7:0] b, output reg [7:0] out, output reg result_is_zer原创 2021-12-03 09:30:22 · 374 阅读 · 0 评论 -
Sim/circuit9
module top_module ( input clk, input a, output [3:0] q ); always @(posedge clk) begin if(a == 1 ) q <= 4; else if (q == 6) q <= 0; else .原创 2021-12-02 22:12:54 · 185 阅读 · 0 评论 -
Sim/circuit8
module top_module ( input clock, input a, output p, output q ); reg state; // for q always @(negedge clock) begin q <= a; end always @(negedge clock) begin state &原创 2021-12-02 22:05:48 · 658 阅读 · 0 评论 -
Exams/2014 q3fsm
做了好久,注意两点1,当cnt_cycle==3是,cnt_w = w,当时的w要记住2,因为cnt_cylce忙于state一个周期module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z); parameter A=0, B=1; reg state, next_state; reg[1:0] cnt_w,原创 2021-12-01 21:11:44 · 204 阅读 · 0 评论 -
Fsm serial
方法一:比较笨的方法module top_module( input clk, input in, input reset, // Synchronous reset output done); //初步定10个状态 parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,s11=11; reg [3:0] state,next_state; alway.原创 2021-11-30 21:06:38 · 169 阅读 · 0 评论 -
Fsm ps2
module top_module( input clk, input [7:0] in, input reset, // Synchronous reset output done); // reg [1:0] state,next_state; parameter byte1=1, byte2=2, byte3=3, none=0; // State transition logic (combinational) always原创 2021-11-30 09:33:05 · 401 阅读 · 0 评论 -
Fsm onehot
module top_module( input in, input [9:0] state, output [9:0] next_state, output out1, output out2); //状态转换 assign next_state[0] = state[0]&~in | state[1]&~in | state[2]&~in | state[3]&~in | state[4]&~in.原创 2021-11-30 09:10:27 · 104 阅读 · 0 评论 -
Lemmings3
module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, input dig, output walk_left, output walk_right, output aaah, output digging .原创 2021-11-29 21:13:49 · 236 阅读 · 0 评论 -
Lemmings2
主要这道题用四个状态控制最好。module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, output walk_left, output walk_right, output aaah ); reg [1:0] .原创 2021-11-29 20:56:38 · 112 阅读 · 0 评论 -
Lemmings1
module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, output walk_left, output walk_right); // // parameter LEFT=0, RIGHT=1, ... reg state, next_stat.原创 2021-11-29 20:34:11 · 119 阅读 · 0 评论 -
Fsm3-hdlbits
module top_module( input clk, input in, input areset, output out); // parameter A=0, B=1, C=2, D=3; reg [3:0] state,next_state; // State transition logic always @(*) begin next_state[A] = state[A]&~.原创 2021-11-29 09:34:16 · 178 阅读 · 0 评论 -
Fsm3onehot
“通过检查得出方程”是什么意思?One-hot 状态机编码保证恰好有一个状态位为 1。这意味着可以通过仅检查一个状态位而不是所有状态位来确定状态机是否处于特定状态。通过检查状态转换图中每个状态的输入边,这导致了状态转换的简单逻辑方程。比如上面的状态机中,状态机如何才能达到状态A?它必须使用两个传入边之一:“当前处于状态 A 且 in=0”或“当前处于状态 C 且 in = 0”。由于 one-hot 编码,用于测试“当前处于状态 A”的逻辑方程只是状态 A 的状态位。这导致状态位 A 的下一个状态的最.原创 2021-11-29 09:23:37 · 1336 阅读 · 0 评论 -
Fsm2s
module top_module( input clk, input reset, // Synchronous reset to OFF input j, input k, output out); // parameter OFF=0, ON=1; reg state, next_state; always @(*) begin case(state) OFF: next_stat.原创 2021-11-28 21:17:45 · 185 阅读 · 0 评论 -
Fsm1-hadlbits
module top_module( input clk, input areset, // Asynchronous reset to state B input in, output out);// parameter A=0, B=1; reg state, next_state; always @(*) begin // This is a combinational always block next_.原创 2021-11-28 20:33:41 · 166 阅读 · 0 评论 -
Conwaylife
module top_module( input clk, input load, input [255:0] data, output [255:0] q ); //组合逻辑计算出下一个转态 //时序电路完成赋值 wire [255:0] q_next; wire [3:0] sum [255:0]; //求和判断 always @(posedge clk) begin .原创 2021-11-28 17:02:21 · 126 阅读 · 0 评论 -
Rule110
module top_module( input clk, input load, input [511:0] data, output [511:0] q ); reg [511:0] q_last; always @(posedge clk) begin if(load) q <= data; else .原创 2021-11-28 15:42:32 · 144 阅读 · 0 评论 -
Rule90
module top_module( input clk, input load, input [511:0] data, output [511:0] q ); reg [511:0] q_last; always @(posedge clk) begin if(load) q <= data; else .原创 2021-11-28 15:32:16 · 92 阅读 · 0 评论 -
Exams/ece241 2013 q12
module top_module ( input clk, input enable, input S, input A, B, C, output Z ); //首先创建一个8位的移位寄存器 reg [7:0] Q; reg [6:0] Q_next; always @(posedge clk) begin Q_next = Q[7:1]; if (ena.原创 2021-11-27 19:22:33 · 734 阅读 · 0 评论 -
Exams/2014 q4b
module top_module ( input [3:0] SW, input [3:0] KEY, output [3:0] LEDR); // //SW to R // clk to KEY[0] // E to KEY[1] // L to KEY[2] // w to KEY [3] MUXDFF ins1(KEY[3], LEDR[3], KEY[1], SW[3], KEY[2], KEY[0], LEDR[3].原创 2021-11-27 17:29:34 · 119 阅读 · 0 评论 -
Exams/m2014 q4k
法一:module top_module ( input clk, input resetn, // synchronous reset input in, output out); wire w1,w2,w3; //声明四个模块 D_flip ins1(clk,in,resetn,w1); D_flip ins2(clk,w1,resetn,w2); D_flip ins3(clk,w2,resetn,w3); D_f.原创 2021-11-27 17:14:40 · 595 阅读 · 0 评论 -
Lfsr32
See Lfsr5 for explanations.Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q); reg [31:0] q_next; always @(原创 2021-11-27 17:01:21 · 290 阅读 · 0 评论 -
Mt2015 lfsr
Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdffWrite the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circ原创 2021-11-27 16:36:37 · 443 阅读 · 0 评论 -
Lfsr5
A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a “tap” are XORed with the output bit to produce its nex原创 2021-11-27 16:21:29 · 179 阅读 · 0 评论 -
Shift18
Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this原创 2021-11-27 15:55:24 · 267 阅读 · 0 评论 -
Rotate100
Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rota原创 2021-11-27 11:36:22 · 174 阅读 · 0 评论 -
Mt2015 muxdff
Taken from ECE253 2015 midterm question 5Consider the sequential circuit below:module top_module ( input clk, input L, input r_in, input q_in, output reg Q); wire w1; Mux2_1 ins1(q_in, r_in,L,w1); flip_flop ins2(w1,clk,Q);endmodulemodul原创 2021-11-24 20:18:05 · 1818 阅读 · 4 评论