目录
一、VGA协议简介
VGA驱动显示器用的是扫描的方式，一般是逐行扫描。
逐行扫描是扫描从屏幕左上角一点开始，从左像右逐点扫描，每扫描完一行,电子束回到屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行同步；
当扫描完所有的行，形成一帧后，用场同步信号进行场同步，并使扫描回到屏幕左上方，同时进行场消隐,开始下一帧。
二、屏幕上显示彩色条纹
代码：
data_gen：
module data_gen(
input wire clk ,
input wire rst_n ,
input wire [10:0] h_addr ,//数据有效显示区域行地址
input wire [10:0] v_addr ,//数据有效显示区域场地址
output reg [23:0] data_disp
);
parameter
BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKYBLUE = 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
//
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_disp <= WHITE;
end
else begin
case(h_addr)
0 : data_disp <= BLACK ;
80 : data_disp <= RED ;
160: data_disp <= GREEN ;
240: data_disp <= BLUE ;
320: data_disp <= YELLOW ;
400: data_disp <= SKYBLUE ;
480: data_disp <= PURPLE ;
560: data_disp <= GRAY ;
default:data_disp <= data_disp ;
endcase
end
end
endmodule
vga_ctrl：
`define vga_640_480
`include "vga_param.v"
module vga_ctrl(
input clk ,//时钟信号 //25.2MHZ
input rst_n ,//复位信号
input [23:0] data_disp ,
output reg [10:0] h_addr ,//数据有效显示区域行地址
output reg [10:0] v_addr ,//数据有效显示区域场地址
output reg vsync ,
output reg hsync ,
output reg [7 :0] vga_r ,
output reg [7 :0] vga_b ,
output reg [7 :0] vga_g ,
output wire vga_blk ,
output wire vga_sync ,
output reg vga_clk //25.2MHZ
);
//参数定义
parameter H_SYNC_START = 1,
H_SYNC_STOP = `H_Sync_Time ,
H_DATA_START = `H_Sync_Time + `H_Back_Porch + `H_Left_Border,
H_DATA_STOP = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time,
V_SYNC_START = 1,
V_SYNC_STOP = `V_Sync_Time,
V_DATA_START = `V_Sync_Time + `V_Back_Porch + `V_Top_Border,
V_DATA_STOP = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
//信号定义
reg [11:0] cnt_h_addr ;//行地址计数器
wire add_h_addr ;
wire end_h_addr ;
reg [11:0] cnt_v_addr ;//长地址计数器
wire add_v_addr ;
wire end_v_addr ;
assign vga_sync = 1'b0;
assign vga_blk = ~((cnt_h_addr<`H_Front_Porch + `H_Sync_Time + `H_Back_Porch)||(cnt_v_addr<`V_Front_Porch + `V_Sync_Time + `V_Back_Porch));
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'd0;
end
else if(add_h_addr)begin
if(end_h_addr)begin
cnt_h_addr <= 12'd0;
end
else begin
cnt_h_addr <= cnt_h_addr + 12'd1;
end
end
else begin
cnt_h_addr <= 12'd0;
end
end
assign add_h_addr = 1'b1;
assign end_h_addr = add_h_addr && cnt_h_addr == `H_Total_Time - 1;
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'd0;
end
else if(add_v_addr)begin
if(end_v_addr)begin
cnt_v_addr <= 12'd0;
end
else begin
cnt_v_addr <= cnt_v_addr + 12'd1;
end
end
else begin
cnt_v_addr <= cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr == `V_Total_Time - 1;
//行场同步信号
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_START - 1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_STOP - 1)begin
hsync <= 1'b1;
end
else begin
hsync <= hsync;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_START - 1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_STOP - 1)begin
vsync <= 1'b1;
end
else begin
vsync <= vsync;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
vga_clk =0;
end
else begin
vga_clk = ~vga_clk;
end
end
//数据有效显示区域定义
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'd0;
end
else if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1))begin
h_addr <= cnt_h_addr - H_DATA_START - 1;
end
else begin
h_addr <= 11'd0;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'd0;
end
else if((cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))begin
v_addr <= cnt_v_addr - V_DATA_START -1;
end
else begin
v_addr <= 11'd0;
end
end
//显示数据
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
end
else if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1)
&& (cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))begin
vga_r <= data_disp[23:16];
vga_g <= data_disp[15: 8];
vga_b <= data_disp[7 : 0];
end
else begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
end
end
endmodule
vga_param：
//vga_Param
//`define vga_480_272
`define vga_640_480
//`define vga_800_480
//`define vga_800_600
//`define vga_1024_600
//`define vga_1024_768
//`define vga_1280_720
//`define vga_1920_1080
`ifdef vga_480_272
`define H_Right_Border 0
`define H_Front_Porch 2
`define H_Sync_Time 41
`define H_Back_Porch 2
`define H_Left_Border 0
`define H_Data_Time 480
`define H_Total_Time 525
`define V_Bottom_Border 0
`define V_Front_Porch 2
`define V_Sync_Time 10
`define V_Back_Porch 2
`define V_Top_Border 0
`define V_Data_Time 272
`define V_Total_Time 286
`elsif vga_640_480
`define H_Right_Border 8
`define H_Front_Porch 8
`define H_Sync_Time 96
`define H_Back_Porch 40
`define H_Left_Border 8
`define H_Data_Time 640
`define H_Total_Time 800
`define V_Bottom_Border 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_Top_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif vga_800_480
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_Back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Total_Time 1056
`define V_Bottom_Border 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_Top_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif vga_800_600
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_Back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Total_Time 1056
`define V_Bottom_Border 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_Top_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif vga_1024_600
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Border 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_Top_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif vga_1024_768
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Border 0
`define V_Front_Porch 3
`define V_Sync_Time 6
`define V_Back_Porch 29
`define V_Top_Border 0
`define V_Data_Time 768
`define V_Total_Time 806
`elsif vga_1280_720
`define H_Right_Border 0
`define H_Front_Porch 110
`define H_Sync_Time 40
`define H_Back_Porch 220
`define H_Left_Border 0
`define H_Data_Time 1280
`define H_Total_Time 1650
`define V_Bottom_Border 0
`define V_Front_Porch 5
`define V_Sync_Time 5
`define V_Back_Porch 20
`define V_Top_Border 0
`define V_Data_Time 720
`define V_Total_Time 750
`elsif vga_1920_1080
`define H_Right_Border 0
`define H_Front_Porch 88
`define H_Sync_Time 44
`define H_Back_Porch 148
`define H_Left_Border 0
`define H_Data_Time 1920
`define H_Total_Time 2200
`define V_Bottom_Border 0
`define V_Front_Porch 4
`define V_Sync_Time 5
`define V_Back_Porch 36
`define V_Top_Border 0
`define V_Data_Time 1080
`define V_Total_Time 1125
`endif
vga_top：
module vga_top(
input clk ,//时钟信号
input rst_n ,//复位信号
output wire vsync ,
output wire hsync ,
output wire [7 :0] vga_r ,
output wire [7 :0] vga_b ,
output wire [7 :0] vga_g ,
output vga_blk ,
output wire vga_sync ,
output vga_clk
);
wire [23:0] data_disp ;
wire [10:0] h_addr ;
wire [10:0] v_addr ;
data_gen u_data_gen(
.clk (vga_clk ),//时钟信号
.rst_n (rst_n ),//复位信号
.h_addr (h_addr ),//数据有效显示区域地址
.v_addr (v_addr ),//数据有效显示区域地址
.data_disp (data_disp )
);
vga_ctrl u_vga_ctrl(
.clk (clk ),//时钟信号 25.2MHZ
.rst_n (rst_n ),//复位信号
.data_disp (data_disp ),
.h_addr (h_addr ),//数据有效显示区域行地址
.v_addr (v_addr ),//数据有效显示区域场地址
.vsync (vsync ),
.hsync (hsync ),
.vga_r (vga_r ),
.vga_b (vga_b ),
.vga_g (vga_g ),
.vga_blk (vga_blk ),
.vga_sync (vga_sync ),
.vga_clk (vga_clk )
);
endmodule
仿真测试：
`timescale 1ns/1ns
`define clk_period 40
module tb();
reg clk ;
reg rst_n ;
wire hsync ;
wire vsync ;
wire vga_blk ;
wire vga_clk ;
wire [07:0] vga_r ;
wire [07:0] vga_g ;
wire [07:0] vga_b ;
//ASCII 显示颜色字符
reg [63:00] CHAR_CLO ;
parameter
BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BULE= 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
always @(*) begin
case(u_vga_top.data_disp)
BLACK : CHAR_CLO = "BLACK ";
RED : CHAR_CLO = "RED ";
GREEN : CHAR_CLO = "GREEN ";
BLUE : CHAR_CLO = "BLUE ";
YELLOW : CHAR_CLO = "YELLOW ";
SKY_BULE : CHAR_CLO = "SKY_BULE";
PURPLE : CHAR_CLO = "PURPLE ";
GRAY : CHAR_CLO = "GRAY ";
WHITE : CHAR_CLO = "WHITE ";
default : CHAR_CLO = "WHITE ";
endcase
end
initial clk = 1'b0;
always #(`clk_period / 2)clk = ~clk;
initial begin
rst_n = 1'b0;
#(`clk_period *20 +3);
rst_n = 1'b1;
#(`clk_period *20)
repeat(2)begin
@(negedge vsync);
end
#(`clk_period * 2000);
$stop;
end
vga_top u_vga_top(
.clk (clk) ,
.rst_n (rst_n) ,
.vsync (vsync) , //
.hsync (hsync) , //
.vga_r (vga_r) , //RGB三色
.vga_g (vga_g) , //
.vga_b (vga_b) , //
.vga_blk (vga_blk) , //VGA消隐信号 ,
.vga_clk (vga_clk) //
);
endmodule
效果显示:
三、字符显示
首先使用字模工具生成汉字字符
再生成数字字模：
这里需要对字模进行一个处理
每一个字四位四位的纵向排列。处理好后
以下是代码部分：
vga_test：
module VGA_test(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)
begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 （X为当前行第几个像素点）
else X<=0; //否则X为0
end
always@(posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 （Y为当前场第几行）
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512时
valid_yr<=1'b0; //行输入冻结
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
wire valid = valid_r; //连线
wire[10:0] x_dis; //像素显示控制信号
wire[10:0] y_dis; //行显示控制信号
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
parameter
char_line00=240'h0000_0100_1020_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
char_line01=240'h1FF0_0100_1020_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
char_line02=240'h1010_3FF8_1020_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
char_line03=240'h1010_0280_1020_07F0_0FE0_0080_0FE0_07E0_1FFC_07E0_07F0_07E0_0FF0_0FF0_0030,
char_line04=240'h1FF0_0440_FDFE_0818_3018_0780_3018_1818_3008_1818_0818_1818_3018_3018_00F0,
char_line05=240'h0000_0820_1020_1000_3818_0180_300C_381C_2010_381C_1000_381C_380C_380C_0170,
char_line06=240'h0000_FFFE_3070_3000_0018_0180_700C_300C_0020_300C_3000_300C_1018_1018_0270,
char_line07=240'h3FF8_0010_3870_37F0_0060_0180_301C_300C_0040_300C_37F0_300C_0018_0018_0C70,
char_line08=240'h0100_0010_54A8_380C_01F0_0180_382C_300C_0080_300C_380C_300C_0060_0060_1070,
char_line09=240'h0100_1F90_50A8_300C_0018_0180_0FCC_300C_0180_300C_300C_300C_0180_0180_2070,
char_line0a=240'hFFFE_1090_9124_300C_000C_0180_001C_300C_0300_300C_300C_300C_0600_0600_7FFE,
char_line0b=240'h0280_1090_1222_300C_380C_0180_0018_3818_0300_3818_300C_3818_0804_0804_0070,
char_line0c=240'h0440_1F90_1420_1818_3018_0180_3830_1C10_0380_1C10_1818_1C10_300C_300C_0070,
char_line0d=240'h0820_0010_1020_07E0_0FE0_0FF8_0FC0_07E0_0300_07E0_07E0_07E0_3FF8_3FF8_03FE,
char_line0e=240'h3018_0050_1020_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
char_line0f=240'hC006_0020_1020_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
reg[7:0] char_bit;
always@(posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd240; //当显示到144像素时准备开始输出图像数据
else if(X>10'd144&&X<10'd384) //左边距屏幕144像素到416像素时 416=144+272（图像宽度）
char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC)
if(X>10'd144&&X<10'd384) //X控制图像的横向显示边界：左边距屏幕左边144像素 右边界距屏幕左边界416像素
begin case(Y) //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000; //如果该行有数据 则颜色为绿色
else vga_rgb<=30'b0000000000_0000000000_0000000000; //否则为黑色
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b0000000000_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; //默认颜色黑色
endcase
end
else vga_rgb<=30'h000000000; //否则黑色
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
由于现在没有DE2-115这块FPGA开发板，所以显示不了效果。
四、总结
做了2个实验，彩条、字符显示，都完成了，就是内容比较多，理解了原理代码也比较好懂，信号的变化和输入输出一定要仔细分析。
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