UVM_学习笔记（一）_简单验证平台的搭建

UVM_学习笔记（一）_简单验证平台搭建

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前言

利用UVM搭建最简单验证平台的搭建。

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DUT

此dut的功能，通过rxd接收数据，在通过txd发送出去，rx_dv是接收数据有效指示，tx_en是发送数据有效指示。即当rx_dv为高时，数据接收成功；tx_en为高时，数据发送成功

module dut(
	input clk,rst_n,
	input [7:0] rxd,
	input rx_dv,
	output reg [7:0] txd,
	output reg tx_en
);
	always@(posedge clk)begin
		if(!rst_n)begin
			txd <= 8'b0;
			tx_en <= 0;
		end
		else begin
			txd <= rxd;
			tx_en <= rx_dv;
		end
	end
endmodule

interface

`ifdef INTERFACE_SV
`define INTERFACE_SV
interface my_if(input clk,input rst_n);
	logic [7:0] data;
	logic valid;
endinterface
`endif

top_tb

`ifdef TOP_TB_SV
`define TOP_TB_SV
`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;
`include "interface.sv"
`include "my_transaction.sv"
module top_tb;
	wire [7:0] txd;
	wire tx_en;
	reg [7:0] rxd;
	reg rx_dv;
	reg clk,rst_n;
	my_if input_if(clk,rst_n);
	my_if output_if(clk,rst_n);
	dut my_dut(
		.clk(clk),
		.rst_n(rst_n),
		.rxd(input_if.data),
		.rx_dv(input_if.valid),
		.txd(output_if.data),
		.tx_en(output_if.valid)
	);
	initial begin
		run_test("base_test");
	end
	initial begin
		`uvm_config_db #(virtual my_if)::set(null,"uvm_test_top.env.i_agt.drv","vif",input_if)
		`uvm_config_db #(virtual my_if)::set(null,"uvm_test_top.env.i_agt.mon","vif",input_if)
		`uvm_config_db #(virtual my_if)::set(null,"uvm_test_top.env.o_agt.mon","vif",output_if)
	end
	initial begin
		clk = 0;
		forever #5 clk = ~clk;
	end
	initial begin
		rst_n = 0;
		#1000 rst_n = 1;
	end
endmodule
`endif

transaction

`ifdef MY_TRANSACTION_SV
`define MY_TRANSACTION_SV
class my_transaction extends uvm_sequence_item;
	function new(string name = "my_transaction");
		super.new(name);
	endfunction
	rand bit [47:0] smac;
	rand bit [47:0] dmac;
	rand bit [15:0] ether_type;
	rand byte pload[];
	rand bit [31:0] crc;
	`uvm_object_utils_begin(my_transaction)
		`uvm_field_int(smac,UVM_ALL_ON)
		`uvm_field_int(dmac,UVM_ALL_ON)
		`uvm_field_int(ether_type,UVM_ALL_ON)
		`uvm_field_array_int(pload