2020-10-03

移位乘法器的verilog

1.程序
module mult(a,b,dout);
input [3:0]a;
input [3:0]b;
output [7:0]dout;
reg [7:0]dout;
integer i;
always@(a or b)
begin
dout=4’b0;
for(i=0;i<4;i=i+1)
if(b[i]==1)
dout=dout+(a<<i);
end
endmodule

2.testbench
`timescale 1 us/ 1 ps
module mult_tb();
reg [3:0] a;
reg [3:0] b;
wire [7:0] dout;

// assign statements (if any)
mult i1 (
// port map - connection between master ports and signals/registers
.a(a),
.b(b),
.dout(dout)
);
initial
begin
a=4’b0000;b=4’b0000;
#10 a=4’b1100;b=4’b0010;
#10 a=4’b1010;b=4’b0100;
#10 a=4’b1010;b=4’b0110;
#10 a=4’b0101;b=4’b0110;
#10 a=4’b0010;b=4’b0010;
#10 a=4’b1100;b=4’b1010;
end
endmodule

3.仿真图